XPC7445 Freescale Semiconductor, XPC7445 Datasheet - Page 6

• Manufacturer Part Number: XPC7445
• Description: RISC Microprocessor Hardware Specifications
• Manufacturer: Freescale Semiconductor

General Parameters
General Parameters
Table 13 provides the L3 bus AC timing specifications for PB2 and Late Write SRAMs for the MPC7455
part numbers described herein.
6
At recommended operating conditions. See Table 4.
L3_CLK rise and fall
time
Setup times:
Input hold times:
Valid times:
Valid times:
Output hold times:
Output hold times:
L3_CLK to high
impedance:
L3_CLK to high
impedance:
Notes:
1. Rise and fall times for the L3_CLK output are measured from 20% to 80% of GV
2. All input specifications are measured from the midpoint of the signal in question to the midpoint voltage of the rising
3. All output specifications are measured from the midpoint voltage of the rising edge of L3_CLKn to the midpoint of
4. t
5. Timing behavior and characterization are currently being evaluated.
6. These configuration bits allow the AC timing of the L3 interface to be altered via software. They must be both set or
Data and parity
Data and parity
Data and parity
All other outputs
Data and parity
All other outputs
Data and parity
All other outputs
edge of the input L3_ECHO_CLKn (see Figure 10 in the MPC7455 RISC Microprocessor Hardware Specifications).
Input timings are measured at the pins.
the signal in question. The output timings are measured at the pins. All output timings assume a purely resistive
50-Ω load (see Figure 10 in the MPC7455 RISC Microprocessor Hardware Specifications).
launched by an internal clock delayed in phase by 90°. Therefore, there is a frequency component to the output valid
and output hold times such that the specified output signal will be valid for approximately one L3_CLK period
starting three-fourths of a clock prior to the edge on which the SRAM will sample it and ending one-fourth of a clock
period after the edge it will be sampled.
both cleared; other configurations will increase t
L3_CLK
Parameter
Table 13. L3 Bus Interface AC Timing Specifications for PB2 and Late Write SRAMs
/4 is one-fourth the period of L3_CLKn. This parameter indicates that the specified output signal is actually
MPC7455 Part Number Specification for the XPC74x5RXnnnNx Series
Symbol
t
t
t
t
t
t
t
t
L3DVEH
L3DXEH
L3CHDV
L3CHOV
L3CHDX
L3CHOX
L3CHOZ
L3CHDZ
t
t
L3CR
L3CF
,
Freescale Semiconductor, Inc.
For More Information On This Product,
L2CR[12]=0 and L3CR[12]=0
t
t
L3_CLK
L3_CLK
Min
1.5
—
—
—
—
—
—
/4 – 0.4
/4 – 0.4
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L3CSKW1
t
t
L3_CLK
L3_CLK
Max
1.0
0.5
2.0
2.0
—
—
—
All Speed Grades
/4 + 1.0
/4 + 1.0
and t
6
L3CSKW2
t
t
L2CR[12]=1 and L3CR[12]=1
L3_CLK
L3_CLK
, which may cause unreliable L3 operation.
Min
1.5
—
—
—
—
—
—
/4 – 0.2
/4 – 0.2
DD
t
t
.
L3_CLK
L3_CLK
Max
1.0
0.5
2.0
2.0
—
—
—
/4 + 1.2
/4 + 1.2
6
Unit Notes
MOTOROLA
ns
ns
ns
ns
ns
ns
ns
ns
ns
3, 4, 5
3, 4, 5
1, 5
2, 5
2, 5
4, 5
4
5
5