GS8162Z36BGD-150 GSI [GSI Technology], GS8162Z36BGD-150 Datasheet
GS8162Z36BGD-150
Related parts for GS8162Z36BGD-150
GS8162Z36BGD-150 Summary of contents
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BGA Commercial Temp Industrial Temp Features • NBT (No Bus Turn Around) functionality allows zero wait Read-Write-Read bus utilization; fully pin-compatible with both pipelined and flow through NtRAM™, NoBL™ and ZBT™ SRAMs • 2 3.3 ...
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Bump BGA—x18 Commom I/O—Top View DDQ D NC DQB V DDQ E NC DQB V DDQ F NC DQB V DDQ G NC DQB ...
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Bump BGA—x36 Common I/O—Top View DQPC NC V DDQ D DQC DQC V DDQ E DQC DQC V DDQ F DQC DQC V DDQ G DQC DQC ...
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GS8162Z36B Pad Out—119-Bump BGA—Top View (Package Rev: 1.04a 2/2006 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. ...
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GS8162Z18B Pad Out—119-Bump BGA—Top View (Package Rev: 1.04a 2/2006 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. ...
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GS8162Z18/36 119-Bump and 165-Bump BGA Pin Description Symbol Type I — ...
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Functional Details Clocking Deassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in ...
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Synchronous Truth Table Operation Type Address CK CKE ADV Read Cycle, Begin Burst R Read Cycle, Continue Burst B NOP/Read, Begin Burst R Dummy Read, Continue Burst B Write Cycle, Begin Burst W Write Cycle, Continue Burst ...
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Pipelined and Flow Through Read Write Control State Diagram New Read R R Burst Read B Key Input Command Code ƒ Transition Current State (n) Next State (n+1) n Clock (CK) Command Current State Current State and Next State Definition ...
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Intermediate B W High Z (Data In) Key Input Command Code ƒ Transition Current State (n) Intermediate State (N+1) Clock (CK) Command Current State and Next State Definition for Rev: 1.04a 2/2006 Specifications cited are subject to change without notice. ...
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B W High Z (Data In) Key Input Command Code ƒ Transition Current State (n) Clock (CK) Command Current State and Next State Definition for: Rev: 1.04a 2/2006 Specifications cited are subject to change without notice. For latest documentation see ...
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Burst Cycles Although NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from read to write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address ...
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Burst Counter Sequences Linear Burst Sequence A[1:0] A[1:0] A[1:0] A[1:0] 1st address 00 01 2nd address 01 10 3rd address 10 11 4th address 11 00 Note: The burst counter wraps to initial state on the 5th clock. Sleep Mode ...
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Absolute Maximum Ratings (All voltages reference Symbol Voltage in V DDQ V I/O V Voltage on Other Input Pins IN I Input Current on Any Pin IN I Output Current on Any I/O ...
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V Range Logic Levels DDQ3 Parameter V Input High Voltage DD V Input Low Voltage DD V I/O Input High Voltage DDQ V I/O Input Low Voltage DDQ Notes: 1. The part numbers of Industrial Temperature Range versions end the ...
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Undershoot Measurement and Timing 50% V – 2 50% tKC Capacitance 2 Parameter Input Capacitance Input/Output Capacitance Note: ...
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DC Electrical Characteristics Parameter Input Leakage Current (except mode pins) ZZ Input Current FT, ZQ Input Current Output Leakage Current Output High Voltage Output High Voltage Output Low Voltage Rev: 1.04a 2/2006 Specifications cited are subject to change without notice. ...
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Operating Currents Parameter Test Conditions Device Selected; All other inputs Operating ≥V or ≤ V Current IH IL Output open Standby ZZ ≥ V – 0 Current Device Deselected; Deselect All other inputs Current ≥ ≤ ...
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AC Electrical Characteristics Parameter Clock Cycle Time Clock to Output Valid Clock to Output Invalid Pipeline Clock to Output in Low-Z Setup time Hold time Clock Cycle Time Clock to Output Valid Clock to Output Invalid Flow Through Clock to ...
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Write A Read CKE ADV Rev: 1.04a 2/2006 Specifications cited are subject to change without notice. For latest documentation ...
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Write A Write CKE ADV A0– D(A) G *Note High(False ...
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JTAG Port Operation Overview The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with ...
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Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when ...
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Tap Controller Instruction Set ID Register Contents Die Revision Code Bit # ...
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Test Logic Reset 1 0 Run Test Idle 0 Instruction Descriptions BYPASS When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This occurs when the TAP controller is moved to ...
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Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command. Then the EXTEST command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output drivers on the ...
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JTAG Port AC Test Conditions Parameter Input high level Input low level Input slew rate Input reference level Output reference level Notes: 1. Include scope and jig capacitance. 2. Test conditions as shown unless otherwise noted. JTAG TAP Instruction Set ...
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JTAG Port Recommended Operating Conditions and DC Characteristics Parameter 3.3 V Test Port Input High Voltage 3.3 V Test Port Input Low Voltage 2.5 V Test Port Input High Voltage 2.5 V Test Port Input Low Voltage TMS, TCK and ...
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JTAG Port AC Electrical Characteristics Parameter Symbol TCK Cycle Time tTKC TCK Low to TDO Valid tTKQ TCK High Pulse Width tTKH TCK Low Pulse Width tTKL TDI & TMS Set Up Time tTS TDI & TMS Hold Time tTH ...
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Package Dimensions—165-Bump FPBGA (Package D) A1 CORNER TOP VIEW SEATING PLANE C Rev: 1.04a ...
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Package Dimensions—119-Bump FPBGA (Package B, Variation 2 A1 TOP VIEW SEATING PLANE C Rev: 1.04a 2/2006 ...
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Ordering Information for GSI Synchronous Burst RAMs 1 Org Part Number GS8162Z18BB-250 GS8162Z18BB-200 GS8162Z18BB-150 512K x 36 GS8162Z36BB-250 512K x 36 GS8162Z36BB-200 512K x 36 GS8162Z36BB-150 GS8162Z18BB-250I 1M ...
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... GS8162Z36BGD-250I 512K x 36 GS8162Z36BGD-200I 512K x 36 GS8162Z36BGD-150I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8162Z36BB-200IT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user ...
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Sync SRAM Datasheet Revision History Types of Changes DS/DateRev. Code: Old; Format or Content New GSxxB_r1 GSxxB_r1; GS8162ZxxB_r1_01 GSxxB_r1_01; GS8162ZxxB_r1_02 GSxxB_r1_02; GS8162ZxxB_r1_03 GSxxB_r1_03; GS8162ZxxB_r1_04 Rev: 1.04a 2/2006 Specifications cited are subject to change without notice. For latest documentation see ...