CY7C373I66JC Cypress Semiconductor Corporation., CY7C373I66JC Datasheet

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CY7C373I66JC

Manufacturer Part Number
CY7C373I66JC
Description
PLCC84
Manufacturer
Cypress Semiconductor Corporation.
Datasheet

Specifications of CY7C373I66JC

Date_code
01+
Cypress Semiconductor Corporation
Document #: 38-03030 Rev. **
Features
Selection Guide
Maximum Propagation Delay
Minimum Set-up, t
Maximum Clock to Output
Typical Supply Current, I
Note:
• 64 macrocells in four logic blocks
• 64 I/O pins
• 5 dedicated inputs including 4 clock pins
• In-System Reprogrammable™ (ISR™) Flash
• Bus Hold capabilities on all I/Os and dedicated inputs
• No hidden delays
• High speed
• Fully PCI compliant
• 3.3V or 5.0V I/O operation
• Available in 84-pin PLCC and 100-pin TQFP packages
• Pin compatible with the CY7C374i
1.
Logic Block Diagram
technology
— JTAG interface
— f
— t
— t
— t
The 3.3V I/O mode timing adder, t
I/O
I/O
MAX
PD
S
CO
16
= 5.5 ns
0
= 10 ns
-I/O
-I/O
= 6.5 ns
= 125 MHz
15
31
16 I/Os
16 I/Os
S
(ns)
CC
[1]
, t
(mA)
[1]
CO
3.3IO
, t
PD
(ns)
, must be added to this specification when V
BLOCK
BLOCK
LOGIC
LOGIC
2
(ns)
32
A
B
MACROCELL
7C373i–125 7C373i–100
3901 North First Street
5.5
6.5
10
75
UltraLogic™ 64-Macrocell Flash CPLD
36
16
36
16
INPUT
INPUT
1
PIM
6.0
6.5
12
75
Functional Description
The CY7C373i is an In-System Reprogrammable Complex
Programmable Logic Device (CPLD) and is part of the
F
all members of the F
signed to bring the ease of use and high performance of the
22V10, as well as PCI Local Bus Specification support, to
high-density CPLDs.
Like all of the UltraLogic™ F
is electrically erasable and In-System Reprogrammable (ISR),
which simplifies both design and manufacturing flows, thereby
reducing costs. The Cypress ISR function is implemented
through a JTAG serial interface. Data is shifted in and out
through the SDI and SDO pins.The ISR interface is enabled
using the programming voltage pin (ISR
cause of the superior routability of the F
often allows users to change existing logic designs while si-
multaneously fixing pinout assignments.
CLOCK
INPUTS
LASH
CCIO
INPUT/CLOCK
MACROCELLS
4
370i™ family of high-density, high-speed CPLDs. Like
36
16
36
16
7C373i–83
= 3.3V.
15
75
San Jose
8
8
BLOCK
BLOCK
LOGIC
LOGIC
32
D
C
7C373iL-83
2
LASH
15
45
8
8
370i family, the CY7C373i is de-
CA 95134
LASH
Revised September 4, 2001
370i devices, the CY7C373i
7C373i–66 7C373iL–66
16 I/Os
16 I/Os
LASH
20
10
10
75
EN
). Additionally, be-
CY7C373i
370i devices, ISR
I/O
I/O
408-943-2600
32
48
7C373i–1
I/O
I/O
47
63
20
10
10
45

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