CY7C68013128AC Cypress Semiconductor Corporation., CY7C68013128AC Datasheet

CY7C68013128AC

Manufacturer Part Number

CY7C68013128AC

Description

QFP-128

Manufacturer

Cypress Semiconductor Corporation.

Datasheet

1.CY7C68013128AC.pdf (48 pages)

Specifications of CY7C68013128AC

Date_code

07+

Current page: 1 of 48
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Cypress Semiconductor Corporation

Document #: 38-08012 Rev. *F

1.0

• Single-chip integrated USB 2.0 Transceiver, SIE, and

• Software: 8051 code runs from:

• Four programmable BULK/INTERRUPT/

• 8- or 16-bit external data interface

• GPIF

• Integrated, industry standard enhanced 8051:

Enhanced 8051 Microprocessor

ISOCHRONOUS endpoints

— Internal RAM, which is downloaded via USB

— Internal RAM, which is loaded from EEPROM

— External memory device (128 pin package

— Buffering options: double, triple and quad

— Allows direct connection to most parallel interface

— Programmable waveform descriptors and configu-

— Supports multiple Ready (RDY) inputs and Control

— Up to 48-MHz clock rate

— Four clocks per instruction cycle

— Two USARTS

— Three counter/timers

— Expanded interrupt system

— Two data pointers

full- and high-speed

ration registers to define waveforms

(CTL) outputs

Integrated

XCVR

EZ-USB FX2 Features

D+

D–

FX2

1.5k

Use EZ-USB FX2LP instead of EZ-USB FX2 for new designs

connected for

full speed

Enhanced USB core

Simplifies 8051 core

XCVR

USB

2.0

Ext. XTAL

x20

PLL

24-MHz

/0.5

/1.0

/2.0

This part is not recommended for new designs

1.1/2.0

Smart

Engine

USB

•

High-performance micro

using standard tools

with lower-power options

Figure 1-1. Block Diagram

four clocks/cycle

3901 North First Street

Easy firmware changes

12/24/48 MHz,

8051 Core

“Soft Configuration”

EZ-USB FX2™ USB Microcontroller

8.5 kB

RAM

• Supports bus-powered applications by using renumer-

• 3.3V operation

• Smart Serial Interface Engine

• Vectored USB interrupts

• Separate data buffers for the SETUP and DATA portions

• Integrated I

• 48-MHz, 24-MHz, or 12-MHz 8051 operation

• Four integrated FIFOs

• Special autovectors for FIFO and GPIF interrupts

• Up to 40 general-purpose I/Os

• Four package options—128-pin TQFP, 100-pin TQFP,

• Four packages are defined for the family: 56 SSOP, 56

ation

of a CONTROL transfer

kHz

56-pin QFN and 56-pin SSOP

QFN, 100 TQFP, and 128 TQFP

— Brings glue and FIFOs inside for lower system cost

— Automatic conversion to and from 16-bit buses

— Master or slave operation

— FIFOs can use externally supplied clock or asyn-

— Easy interface to ASIC and DSP ICs

chronous strobes

•

FIFO and endpoint memory

(master or slave operation)

Additional I/Os (24)

San Jose

C-compatible controller, runs at 100 or 400

Compatible

GPIF

FIFO

4 kB

Master

ADDR (9)

RDY (6)

CTL (6)

CA 95134

8/16

Revised April 25, 2005

including two USARTS

standards such as

Up to 96 MBytes/s

ATAPI, EPP, etc.

programmable I/F

to ASIC/DSP or bus

Abundant I/O

General

burst rate

•

CY7C68013

408-943-2600

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