PCA9515ADP118

Manufacturer Part NumberPCA9515ADP118
DescriptionTSSOP8
ManufacturerNXP Semiconductors
PCA9515ADP118 datasheet
 


Specifications of PCA9515ADP118

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PCA9515A
2
I
C-bus repeater
Rev. 04 — 11 April 2008
1. General description
The PCA9515A is a CMOS integrated circuit intended for application in I
SMBus systems.
While retaining all the operating modes and features of the I
extension of the I
enabling two buses of 400 pF.
2
The I
C-bus capacitance limit of 400 pF restricts the number of devices and bus length.
Using the PCA9515A enables the system designer to isolate two halves of a bus, thus
more devices or longer length can be accommodated. It can also be used to run two
buses, one at 5 V and the other at 3.3 V or a 400 kHz and 100 kHz bus, where the
100 kHz bus is isolated when 400 kHz operation of the other is required.
Two or more PCA9515As cannot be put in series. The PCA9515A design does not
allow this configuration. Since there is no direction pin, slightly different ‘legal’ low voltage
levels are used to avoid lock-up conditions between the input and the output. A ‘regular
LOW’ applied at the input of a PCA9515A will be propagated as a ‘buffered LOW’ with a
slightly higher value. When this ‘buffered LOW’ is applied to another PCA9515A,
PCA9516A or PCA9518/A in series, the second PCA9515A, PCA9516A or PCA9518/A
will not recognize it as a ‘regular LOW’ and will not propagate it as a ‘buffered LOW’ again.
The PCA9510/A, PCA9511/A, PCA9512/A, PCA9513/A, PCA9514/A cannot be used in
series with the PCA9515A, PCA9516A or PCA9518/A, but can be used in series with
themselves since they use shifting instead of static offsets to avoid lock-up conditions.
The output pull-down of each internal buffer is set for approximately 0.5 V, while the input
threshold of each internal buffer is set about 0.07 V lower, when the output is internally
driven LOW. This prevents a lock-up condition from occurring.
2. Features
I
2-channel, bidirectional buffer
I
2
I
C-bus and SMBus compatible
I
Active HIGH repeater enable input
I
Open-drain input/outputs
I
Lock-up free operation
I
Supports arbitration and clock stretching across the repeater
I
Accommodates Standard-mode and Fast-mode I
I
Powered-off high-impedance I
I
Operating supply voltage range of 2.3 V to 3.6 V
I
5.5 V tolerant I
2
C-bus by buffering both the data (SDA) and the clock (SCL) lines, thus
2
C-bus pins
2
C-bus and enable pins
Product data sheet
2
C-bus and
2
C-bus system, it permits
2
C-bus devices and multiple masters