74LVC573AD,118 NXP Semiconductors, 74LVC573AD,118 Datasheet - Page 2

• Manufacturer Part Number: 74LVC573AD,118
• Description: IC OCTAL D TRANSP LATCH 20SOIC
• Manufacturer: NXP Semiconductors
• Series: 74LVCr

Specifications of 74LVC573AD,118

• Logic Type: D-Type Transparent Latch
• Package / Case: 20-SOIC (7.5mm Width)
• Circuit: 8:8
• Output Type: Tri-State
• Voltage - Supply: 2.7 V ~ 3.6 V
• Independent Circuits: 1
• Delay Time - Propagation: 1.5ns
• Current - Output High, Low: 24mA, 24mA
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Number Of Circuits: 8
• Logic Family: LVC
• Polarity: Non-Inverting
• Input Bias Current (max): 0.1 uA
• High Level Output Current: - 24 mA
• Low Level Output Current: 24 mA
• Propagation Delay Time: 3.4 ns at 3.3 V
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 1.2 V
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-4620-2; 74LVC573AD-T; 74LVC573AD-T; 935219000118

Philips Semiconductors
FEATURES
DESCRIPTION
The 74LVC573A is a high-performance, low-power,
low-voltage, Si-gate CMOS device, superior to most
advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 or 5 V devices. In
3-state operation, outputs can handle 5 V. This feature
allows the use of these devices as translators in a mixed
3.3 or 5 V environment.
QUICK REFERENCE DATA
Notes
1. C
2. The condition is V
2003 Oct 03
t
C
C
PHL
5 V tolerant inputs/outputs, for interfacing with 5 V logic
Supply voltage range from 1.2 to 3.6 V
Inputs accept voltages up to 5.5 V
CMOS low power consumption
Direct interface with TTL levels
High impedance when V
Flow-through pin-out architecture
Complies with JEDEC standard no. 8-1A
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V
Specified from 40 to +85 C and 40 to +125 C.
I
PD
Octal D-type transparent latch with 5 V
tolerant inputs/outputs; 3-state
P
f
f
C
V
N = total load switching outputs;
SYMBOL
i
o
/t
(C
D
CC
PD
= input frequency in MHz;
L
PLH
= output frequency in MHz;
= output load capacitance in pF;
= C
L
is used to determine the dynamic power dissipation (P
= supply voltage in Volts;
PD
V
CC
2
V
CC
f
propagation delay
input capacitance
power dissipation capacitance per latch notes 1 and 2
o
2
) = sum of the outputs.
Dn to Qn
LE to Qn
I
f
= GND to V
i
CC
N + (C
= 0 V
PARAMETER
L
CC
.
V
CC
2
f
o
) where:
2
C
The 74LVC573A is an octal D-type transparent latch
featuring separate D-type inputs for each latch and 3-state
outputs for bus-oriented applications. A Latch Enable (LE)
input and an Output Enable (OE) input are common to all
internal latches.
The 74LVC573A consists of eight D-type transparent
latches with 3-state true outputs. When LE is HIGH, data
at the Dn inputs enters the latches. In this condition, the
latches are transparent, i.e. a latch output will change each
time its corresponding D-input changes. When LE is LOW,
the latches store the information that was present at the
D-inputs one set-up time preceding the HIGH-to-LOW
transition of LE. When OE is LOW, the contents of the
eight latches are available at the outputs. When OE is
HIGH, the outputs go to the high impedance OFF-state.
Operation of the OE input does not affect the state of the
latches.
The 74LVC573A is functionally identical to the
74LVC373A, but the 74LVC373A has a different pin
arrangement.
L
D
= 50 pF; V
in W).
CONDITIONS
CC
= 3.3 V
3.4
3.1
5.0
15
TYPICAL
Product specification
74LVC573A
ns
ns
pF
pF
UNIT