74LV259DB,118 NXP Semiconductors, 74LV259DB,118 Datasheet
74LV259DB,118
Specifications of 74LV259DB,118
74LV259DB-T
935166060118
Related parts for 74LV259DB,118
74LV259DB,118 Summary of contents
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Rev. 03 — 2 January 2008 1. General description The 74LV259 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC259 and 74HCT259. The 74LV259 is a high-speed 8-bit addressable latch designed ...
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... NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name 74LV259N +125 C 74LV259D +125 C 74LV259DB +125 C 74LV259PW +125 C 74LV259BQ +125 C 4. Functional diagram 001aah118 Fig 1. Logic symbol 74LV259_3 Product data sheet Description DIP16 plastic dual in-line package; 16 leads (300 mil) SO16 plastic small outline package ...
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... NXP Semiconductors Fig 3. Functional diagram 5. Pinning information 5.1 Pinning 74LV259 GND Fig 4. Pin configuration DIP16, SO16 and (T)SSOP16 5.2 Pin description Table 2. Pin description Symbol Pin GND 8 Q[0: 10, 11, 12 74LV259_3 Product data sheet DECODER LATCHES 001aah127 (1) The die substrate is attached to this pad using Fig 5. Pin confi ...
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... NXP Semiconductors Table 2. Pin description …continued Symbol Pin Functional description Table 3. Mode select table H = HIGH voltage level LOW voltage level Table 4. Function table H = HIGH voltage level LOW voltage level don’t care High or LOW data one set-up time prior to the LOW-to-HIGH LE transition; q<n> = state of the output established during the last cycle in which it was addressed or cleared ...
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... NXP Semiconductors 7. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter V supply voltage CC I input clamping current IK I output clamping current OK I output current O I supply current CC I ground current ...
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... NXP Semiconductors 9. Static characteristics Table 7. Static characteristics Voltages are referenced to GND (ground = 0 V). Symbol Parameter V HIGH-level input voltage IH V LOW-level input voltage IL V HIGH-level output voltage OH V LOW-level output voltage OL I input leakage current I I supply current CC I additional supply current ...
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... NXP Semiconductors 10. Dynamic characteristics Table 8. Dynamic characteristics GND = 0 V; For test circuit see Figure Symbol Parameter Conditions t propagation delay D to Qn; see propagation delay An to Qn; see propagation delay HIGH to LOW MR to Qn; PHL propagation delay pulse width LE, HIGH or LOW; see pulse width MR, LOW ...
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... NXP Semiconductors Table 8. Dynamic characteristics GND = 0 V; For test circuit see Figure Symbol Parameter Conditions t set-up time LE; see su Figure hold time D to LE; see hold time An to LE; see power dissipation capacitance V = GND [1] Typical values are measured the same as t and PLH ...
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... NXP Semiconductors 11. Waveforms D input LE input Qn output Measurement points are given in V and V are typical voltage output levels that occur with the output load Fig 6. The enable input (LE) to output (Qn) propagation delays and the enable input pulse width Measurement points are given in ...
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... NXP Semiconductors Measurement points are given in V and V are typical voltage output levels that occur with the output load Fig 9. The conditional reset input (MR) to output (Qn) propagation delays LE input D input Qn output Measurement points are given in V and V are typical voltage output levels that occur with the output load. ...
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... NXP Semiconductors Table 9. Measurement points Supply voltage V CC < 2 3.6 V Test data is given in Table 10. Definitions test circuit Termination resistance should be equal to output impedance Load resistance Load capacitance including jig and probe capacitance. L Fig 12. Load circuit for switching times Table 10. ...
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... NXP Semiconductors 12. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions UNIT max. min. max. mm 4.2 0.51 3.2 inches 0.17 0.02 0.13 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...
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... NXP Semiconductors SO16: plastic small outline package; 16 leads; body width 3 pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.069 0.01 0.004 0.049 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...
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... NXP Semiconductors SSOP16: plastic shrink small outline package; 16 leads; body width 5 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.21 1. 0.25 0.05 1.65 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION IEC SOT338-1 Fig 15. Package outline SOT338-1 (SSOP16) ...
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... NXP Semiconductors TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 x 3.5 x 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... Document ID Release date 74LV259_3 20080102 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Section • Section • ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Functional description . . . . . . . . . . . . . . . . . . . 4 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12 13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 17 14 Revision history ...