74HC259D,652 NXP Semiconductors, 74HC259D,652 Datasheet - Page 2

• Manufacturer Part Number: 74HC259D,652
• Description: IC ADDRESSABLE LATCH 8BIT 16SOIC
• Manufacturer: NXP Semiconductors
• Series: 74HCr

Specifications of 74HC259D,652

• Logic Type: D-Type, Addressable
• Circuit: 1:8
• Output Type: Standard
• Voltage - Supply: 2 V ~ 6 V
• Independent Circuits: 1
• Delay Time - Propagation: 17ns
• Current - Output High, Low: 5.2mA, 5.2mA
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-1426-5; 74HC259D; 933714650652

Philips Semiconductors
FEATURES
GENERAL DESCRIPTION
The 74HC/HCT259 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT259 are high-speed 8-bit addressable
latches designed for general purpose storage applications
in digital systems. The “259” are multifunctional devices
QUICK REFERENCE DATA
GND = 0 V; T
Notes
1. C
2. For HC the condition is V
December 1990
SYMBOL
t
t
C
C
PHL/
PHL
Combines demultiplexer and 8-bit latch
Serial-to-parallel capability
Output from each storage bit available
Random (addressable) data entry
Easily expandable
Common reset input
Useful as a 3-to-8 active HIGH decoder
Output capability: standard
I
8-bit addressable latch
I
PD
CC
f
f
C
V
For HCT the condition is V
i
o
CC
PD
= input frequency in MHz
L
t
category: MSI
= output frequency in MHz
(C
PLH
= output load capacitance in pF
P
= supply voltage in V
is used to determine the dynamic power dissipation (P
L
D
= C
V
amb
CC
PD
PARAMETER
propagation delay
input capacitance
power dissipation capacitance per latch
2
D to Q
A
MR to Q
= 25 C; t
n
, LE to Q
V
f
o
CC
) = sum of outputs
2
n
n
f
r
i
= t
n
I
I
f
= GND to V
= GND to V
= 6 ns
(C
L
V
CC
2
CC
CC
f
o
) where:
1.5 V
CONDITIONS
C
notes 1 and 2
L
2
= 15 pF; V
capable of storing single-line data in eight addressable
latches, and also 3-to-8 decoder and demultiplexer, with
active HIGH outputs (Q
The “259” also incorporates an active LOW common reset
(MR) for resetting all latches, as well as, an active LOW
enable input (LE).
The “259” has four modes of operation as shown in the
mode select table. In the addressable latch mode, data on
the data line (D) is written into the addressed latch. The
addressed latch will follow the data input with all
non-addressed latches remaining in their previous states.
In the memory mode, all latches remain in their previous
states and are unaffected by the data or address inputs.
In the 3-to-8 decoding or demultiplexing mode, the
addressed output follows the state of the D input with all
other outputs in the LOW state. In the reset mode all
outputs are LOW and unaffected by the address (A
and data (D) input. When operating the “259” as an
addressable latch, changing more than one bit of address
could impose a transient-wrong address. Therefore, this
should only be done while in the memory mode. The mode
select table summarizes the operations of the “259”.
D
in W):
CC
= 5 V
0
HC
18
17
15
3.5
19
to Q
7
TYPICAL
), functions are available.
74HC/HCT259
Product specification
HCT
20
20
20
3.5
19
UNIT
ns
ns
ns
pF
pF
0
to A
2
)