74ALVCH16373DTR ON Semiconductor, 74ALVCH16373DTR Datasheet

74ALVCH16373DTR

Manufacturer Part Number

74ALVCH16373DTR

Description

IC LATCH TRANSPRNT 16BIT 48TSSOP

Manufacturer

ON Semiconductor

Series

74ALVCHr

Datasheet

1.74ALVCH16373DTR.pdf (10 pages)

Specifications of 74ALVCH16373DTR

Logic Type

D-Type Transparent Latch

Circuit

8:8

Output Type

Tri-State

Voltage - Supply

2.3 V ~ 3.6 V

Independent Circuits

Delay Time - Propagation

1ns

Current - Output High, Low

24mA, 24mA

Operating Temperature

-40°C ~ 85°C

Mounting Type

Surface Mount

Package / Case

48-TSSOP

Lead Free Status / RoHS Status

Contains lead / RoHS non-compliant

Other names

74ALVCH16373DTROS

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74ALVCH16373

Low−Voltage 16−Bit

Transparent Latch with Bus

Hold 1.8/2.5/3.3 V

(3−State, Non−Inverting)

16−bit transparent latch. It is designed for very high−speed, very

low−power operation in 1.8 V, 2.5 V or 3.3 V systems. The

VCXH16373 is byte controlled, with each byte functioning

identically, but independently. Each byte has separate Output Enable

and Latch Enable inputs. These control pins can be tied together for

full 16−bit operation.

3.6 V−tolerant outputs. When the Latch Enable (LEn) inputs are

HIGH, data on the Dn inputs enters the latches. In this condition, the

latches are transparent, (a latch output will change state each time its D

input changes). When LE is LOW, the latch stores the information that

was present on the D inputs a setup time preceding the

HIGH−to−LOW transition of LE. The 3−state outputs are controlled

by the Output Enable (OEn) inputs. When OE is LOW, the outputs are

enabled. When OE is HIGH, the standard outputs are in the high

impedance state, but this does not interfere with new data entering into

the latches. The data inputs include active bushold circuitry,

eliminating the need for external pull−up resistors to hold unused or

floating inputs at a valid logic state.

•

†To ensure the outputs activate in the 3−state condition, the output enable pins

June, 2006 − Rev. 2

should be connected to V

determined by the current sinking capability of the output connected to the OE pin.

The 74ALVCH16373 is an advanced performance, non−inverting

The 74ALVCH16373 contains 16 D−type latches with 3−state

Logic State

Substantially Reduces System Power Requirements

Second Source to Industry Standard 74ALVCH16373

Designed for Low Voltage Operation: V

3.6 V Tolerant Inputs and Outputs

High Speed Operation: 3.6 ns max for 3.0 to 3.6 V

Static Drive: ±24 mA Drive at 3.0 V

Supports Live Insertion and Withdrawal

Includes Active Bushold to Hold Unused or Floating Inputs at a Valid

Near Zero Static Supply Current in All Three Logic States (40 mA)

Latchup Performance Exceeds ±250 mA @ 125°C

ESD Performance: Human Body Model >2000V; Machine Model >200V

OFF

Specification Guarantees High Impedance When V

±12 mA Drive at 2.3 V

±4 mA Drive at 1.65 V

through a pull−up resistor. The value of the resistor is

4.5 ns max for 2.3 to 2.7 V

6.8 ns max for 1.65 to 1.95 V

= 1.65 − 3.6 V

= 0 V

†

PIN NAMES

74ALVCH16373DTR

Pins

OEn

LEn

D0−D15

O0−O15

DT SUFFIX

CASE 1201

TSSOP−48

Device

ORDERING INFORMATION

Location

http://onsemi.com

Function

Output Enable Inputs

Latch Enable Inputs

Inputs

Outputs

Package

= Assembly

= Wafer Lot

= Year

= Work Week

TSSOP

Publication Order Number:

MARKING DIAGRAM

74ALVCH16373DT

AWLYYWW

74ALVCH16373/D

2500/Tape & Reel

Shipping

Related parts for 74ALVCH16373DTR

74ALVCH16373DTR Summary of contents

Page 1

... OE pin. © Semiconductor Components Industries, LLC, 2006 June, 2006 − Rev SUFFIX CASE 1201 PIN NAMES Pins OEn LEn = 1.65 − 3 D0−D15 O0−O15 74ALVCH16373DTR † http://onsemi.com MARKING DIAGRAM 48 74ALVCH16373DT 1 AWLYYWW TSSOP− ...

Page 2

OE1 LE1 GND GND ...

Page 3

MAXIMUM RATINGS (Note 1) Symbol V DC Supply Voltage Input Voltage Output Voltage Input Diode Current Output Diode Current Output Sink Current ...

Page 4

DC ELECTRICAL CHARACTERISTICS Symbol Parameter V HIGH Level Input Voltage IH (Note 8) V LOW Level Input Voltage IL (Note 8) V HIGH Level Output Voltage OH V LOW Level Output Voltage OL I Input Leakage Current I I Minimum ...

Page 5

AC CHARACTERISTICS (Note 10 Symbol Parameter t Propagation Delay PLH PHL t Propagation Delay PLH PHL t Output Enable Time to PZH t High and Low Level PZL t Output ...

Page 6

Vm OEn t t PZH PHZ PZL PLZ On Vm WAVEFORM 2 − OUTPUT ENABLE AND DISABLE TIMES 2.0 ns, 10 MHz Symbol V ...

Page 7

SEE NOTE 2 FOR MACHINE REFERENCE ONLY INCLUDING DRAFT AND RADII CONCENTRIC AROUND B R MIN TAPE AND COMPONENTS SHALL PASS AROUND RADIUS R" WITHOUT DAMAGE BENDING RADIUS MAXIMUM COMPONENT ROTATION 10° TYPICAL COMPONENT CAVITY ...

Page 8

MIN (0.06") 20.2 mm MIN A (0.795") FULL RADIUS Figure 8. Reel Dimensions REEL DIMENSIONS Tape Size A Max 24 mm 360 mm 24 2.0 mm, −0.0 (14.173") (0.961" + 0.078", −0.00) DIRECTION OF FEED BARCODE ...

Page 9

TAPE TRAILER (Connected to Reel Hub) NO COMPONENTS CAVITY TOP TAPE 160 mm MIN TAPE K É É É É É É É É É É É É É É L É É É É É É É É É ...

Page 10

... Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303− ...

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