GS88136BD-250IV GSI Technology, GS88136BD-250IV Datasheet

GS88136BD-250IV

Manufacturer Part Number

GS88136BD-250IV

Description

Manufacturer

GSI Technology

Datasheet

1.GS88136BGT-250V.pdf (36 pages)

Specifications of GS88136BD-250IV

Pack_quantity

Comm_code

85423245

Lead_time

Current page: 1 of 36
Download datasheet (2Mb)

100-pin TQFP & 165-bump BGA

Commercial Temp

Industrial Temp

Features

• IEEE 1149.1 JTAG-compatible Boundary Scan

• 1.8 V or 2.5 V +10%/–10% core power supply

• 1.8 V or 2.5 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Byte Write (BW) and/or Global Write (GW) operation

• Internal self-timed write cycle

• Automatic power-down for portable applications

• JEDEC-standard 100-lead TQFP and 165-bump BGA

• RoHS-compliant 100-lead TQFP and 165-bump BGA

Functional Description

Applications

The GS88118/32/36B(T/D)-xxxV is a 9,437,184-bit high

performance synchronous SRAM with a 2-bit burst address

counter. Although of a type originally developed for Level 2

Cache applications supporting high performance CPUs, the

device now finds application in synchronous SRAM

applications, ranging from DSP main store to networking chip

set support.

Controls

Addresses, data I/Os, chip enable (E1, E2), address burst

control inputs (ADSP, ADSC, ADV) and write control inputs

(Bx, BW, GW) are synchronous and are controlled by a

positive-edge-triggered clock input (CK). Output enable (G)

and power down control (ZZ) are asynchronous inputs. Burst

cycles can be initiated with either ADSP or ADSC inputs. In

Burst mode, subsequent burst addresses are generated

internally and are controlled by ADV. The burst address

counter may be configured to count in either linear or

Rev: 1.02 6/2007

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

packages

packages available

Flow Through

Pipeline

3-1-1-1

2-1-1-1

512K x 18, 256K x 32, 256K x 36

Curr (x32/x36)

9Mb Sync Burst SRAMs

Curr (x18)

tCycle

Paramter Synopsis

1/36

interleave order with the Linear Burst Order (LBO) input. The

Burst function need not be used. New addresses can be loaded

on every cycle with no degradation of chip performance.

Flow Through/Pipeline Reads

The function of the Data Output register can be controlled by

the user via the FT mode pin (Pin 14). Holding the FT mode

pin low places the RAM in Flow Through mode, causing

output data to bypass the Data Output Register. Holding FT

high places the RAM in Pipeline mode, activating the rising-

edge-triggered Data Output Register.

SCD Pipelined Reads

The GS88118/32/36B(T/D)-xxxV is a SCD (Single Cycle

Deselect) pipelined synchronous SRAM. DCD (Dual Cycle

Deselect) versions are also available. SCD SRAMs pipeline

deselect commands one stage less than read commands. SCD

RAMs begin turning off their outputs immediately after the

deselect command has been captured in the input registers.

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the Byte Write

control inputs.

Sleep Mode

Low power (Sleep mode) is attained through the assertion

(High) of the ZZ signal, or by stopping the clock (CK).

Memory data is retained during Sleep mode.

Core and Interface Voltages

The GS88118/32/36B(T/D)-xxxV operates on a 1.8 V or 2.5 V

power supply. All input are 1.8 V and 2.5 V compatible.

Separate output power (V

output noise from the internal circuits and are 1.8 V and 2.5 V

compatible.

-250

200

230

160

185

3.0

4.0

5.5

-200

170

195

140

160

3.0

5.0

6.5

-150

140

160

128

145

3.8

6.7

7.5

DDQ

GS88118/32/36B(T/D)-xxxV

) pins are used to decouple

Unit

250 MHz–150 MHz

1.8 V or 2.5 V V

1.8 V or 2.5 V I/O

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