GS881Z36CGD-150V GSI Technology, GS881Z36CGD-150V Datasheet

GS881Z36CGD-150V

Manufacturer Part Number

GS881Z36CGD-150V

Description

PBGA 165/256K X 36 ZBT SRAM, 7.5 ns

Manufacturer

GSI Technology

Datasheet

1.GS881Z36CD-150IV.pdf (37 pages)

Specifications of GS881Z36CGD-150V

Pack_quantity

144

Comm_code

85423245

Lead_time

Current page: 1 of 37
Download datasheet (2Mb)

100-Pin TQFP & 165-Bump BGA

Commercial Temp

Industrial Temp

Features

• User-configurable Pipeline and Flow Through mode

• NBT (No Bus Turn Around) functionality allows zero wait

• Fully pin-compatible with both pipelined and flow through

• IEEE 1149.1 JTAG-compatible Boundary Scan

• 1.8 V or 2.5 V core power supply

• 1.8 V or 2.5 V I/O supply

• LBO pin for Linear or Interleave Burst mode

• Pin-compatible with 2M, 4M, and 18M devices

• Byte write operation (9-bit Bytes)

• 3 chip enable signals for easy depth expansion

• ZZ pin for automatic power-down

• JEDEC-standard packages

• RoHS-compliant 100-lead TQFP and 165-bump BGA

Functional Description

The GS881Z18/32/36C(T/D)-xxxV is a 9Mbit Synchronous

Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL

or other pipelined read/double late write or flow through read/

single late write SRAMs, allow utilization of all available bus

bandwidth by eliminating the need to insert deselect cycles

when the device is switched from read to write cycles.

Rev: 1.00 4/2008

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

read-write-read bus utilization

NtRAM™, NoBL™ and ZBT™ SRAMs

packages available

Flow Through

Pipeline

3-1-1-1

2-1-1-1

9Mb Pipelined and Flow Through

Curr (x32/x36)

Synchronous NBT SRAM

Curr (x18)

tCycle

Paramter Synopsis

1/37

Because it is a synchronous device, address, data inputs, and

read/ write control inputs are captured on the rising edge of the

input clock. Burst order control (LBO) must be tied to a power

rail for proper operation. Asynchronous inputs include the

Sleep mode enable, ZZ and Output Enable. Output Enable can

be used to override the synchronous control of the output

drivers and turn the RAM's output drivers off at any time.

Write cycles are internally self-timed and initiated by the rising

edge of the clock input. This feature eliminates complex off-

chip write pulse generation required by asynchronous SRAMs

and simplifies input signal timing.

The GS881Z18/32/36C(T/D)-xxxV may be configured by the

user to operate in Pipeline or Flow Through mode. Operating

as a pipelined synchronous device, in addition to the rising-

edge-triggered registers that capture input signals, the device

incorporates a rising-edge-triggered output register. For read

cycles, pipelined SRAM output data is temporarily stored by

the edge triggered output register during the access cycle and

then released to the output drivers at the next rising edge of

clock.

The GS881Z18/32/36C(T/D)-xxxV is implemented with GSI's

high performance CMOS technology and is available in

JEDEC-standard 100-pin TQFP and 165-bump BGA packages.

-250

200

230

160

185

3.0

4.0

5.5

-200

170

195

140

160

3.0

5.0

6.5

-150

140

160

128

145

3.8

6.7

7.5

GS881Z18/32/36C(T/D)-xxxV

Unit

250 MHz–150 MHz

1.8 V or 2.5 V V

1.8 V or 2.5 V I/O

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