GS88218CGB-150 GSI Technology, GS88218CGB-150 Datasheet

GS88218CGB-150

Manufacturer Part Number

GS88218CGB-150

Description

BGA 119

Manufacturer

GSI Technology

Datasheet

1.GS88218CB-150I.pdf (38 pages)

Specifications of GS88218CGB-150

Pack_quantity

Comm_code

85423245

Lead_time

Current page: 1 of 38
Download datasheet (2Mb)

119- and 165-Bump BGA

Commercial Temp

Industrial Temp

Features

• FT pin for user-configurable flow through or pipeline operation

• Single/Dual Cycle Deselect selectable

• IEEE 1149.1 JTAG-compatible Boundary Scan

• On-chip read parity checking; even or odd selectable

• ZQ mode pin for user-selectable high/low output drive

• 2.5 V or 3.3 V +10%/–10% core power supply

• 2.5 V or 3.3 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to SCD x18/x36 Interleaved Pipeline mode

• Byte Write (BW) and/or Global Write (GW) operation

• Internal self-timed write cycle

• Automatic power-down for portable applications

• JEDEC-standard 119- and 165-bump BGA packages

• RoHS-Compliant 119-bump and 165-bump BGA packages

Functional Description

Applications

The GS88218/36C is a 9,437,184-bit high performance

synchronous SRAM with a 2-bit burst address counter. Although

of a type originally developed for Level 2 Cache applications

supporting high performance CPUs, the device now finds

application in synchronous SRAM applications, ranging from

DSP main store to networking chip set support.

Controls

Addresses, data I/Os, chip enable (E1), address burst control

inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW,

GW) are synchronous and are controlled by a positive-edge-

triggered clock input (CK). Output enable (G) and power down

control (ZZ) are asynchronous inputs. Burst cycles can be initiated

with either ADSP or ADSC inputs. In Burst mode, subsequent

burst addresses are generated internally and are controlled by

ADV. The burst address counter may be configured to count in

either linear or interleave order with the Linear Burst Order (LBO)

input. The Burst function need not be used. New addresses can be

loaded on every cycle with no

Rev: 1.00 9/2008

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

available

Flow Through

Pipeline

3-1-1-1

2-1-1-1

degradation of chip performance.

9Mb SCD/DCD Sync Burst SRAMs

Curr (x32/x36)

Curr (x18)

tCycle

512K x 18, 256K x 36

Paramter Synopsis

1/38

-333

TBD

2.5

3.0

4.5

-300

Flow Through/Pipeline Reads

The function of the Data Output register can be controlled by the

user via the FT mode . Holding the FT mode pin low places the

RAM in Flow Through mode, causing output data to bypass the

Data Output Register. Holding FT high places the RAM in

Pipeline mode, activating the rising-edge-triggered Data Output

SCD and DCD Pipelined Reads

The GS88218/36C88218/36C is a SCD (Single Cycle

Deselect) and DCD (Dual Cycle Deselect) pipelined

synchronous SRAM. DCD SRAMs pipeline disable commands

to the same degree as read commands. SCD SRAMs pipeline

deselect commands one stage less than read commands. SCD

RAMs begin turning off their outputs immediately after the

deselect command has been captured in the input registers.

DCD RAMs hold the deselect command for one full cycle and

then begin turning off their outputs just after the second rising

edge of clock. The user may configure this SRAM for either

mode of operation using the SCD mode input.

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the Byte Write

control inputs.

FLXDrive™

The ZQ pin allows selection between high drive strength (ZQ low)

for multi-drop bus applications and normal drive strength (ZQ

floating or high) point-to-point applications. See the Output Driver

Characteristics chart for details.

Sleep Mode

Low power (Sleep mode) is attained through the assertion

(High) of the ZZ signal, or by stopping the clock (CK).

Memory data is retained during Sleep mode.

Core and Interface Voltages

The GS88218/36C operates on a 2.5 V or 3.3 V power supply.

All input are 3.3 V and 2.5 V compatible. Separate output

power (V

internal circuits and are 3.3 V and 2.5 V compatible.

TBD

2.5

3.3

5.0

-250

TBD

2.5

4.0

5.5

DDQ

GS88218/36CB/D-333/300/250/200/150

) pins are used to decouple output noise from the

-200

TBD

3.0

5.0

6.5

-150

TBD

3.8

6.7

7.5

Unit

333 MHz–150 MHz

2.5 V or 3.3 V V

2.5 V or 3.3 V I/O

Preliminary

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