GS882Z36CD-300M GSI Technology, GS882Z36CD-300M Datasheet

GS882Z36CD-300M

Manufacturer Part Number

GS882Z36CD-300M

Description

BGA 165/256K x 36 (9 Meg) NBT C Rev

Manufacturer

GSI Technology

Datasheet

1.GS882Z36CB-300M.pdf (33 pages)

Specifications of GS882Z36CD-300M

Pack_quantity

144

Comm_code

85423245

Lead_time

Current page: 1 of 33
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119-bump and 165-bump BGA

Military Temp

Features

• Military Temperature Range

• NBT (No Bus Turn Around) functionality allows zero wait

• 2.5 V or 3.3 V +10%/–10% core power supply

• 2.5 V or 3.3 V I/O supply

• User-configurable Pipeline and Flow Through mode

• ZQ mode pin for user-selectable high/low output drive

• IEEE 1149.1 JTAG-compatible Boundary Scan

• LBO pin for Linear or Interleave Burst mode

• Pin-compatible with 2M, 4M, and 18M devices

• Byte write operation (9-bit Bytes)

• 3 chip enable signals for easy depth expansion

• ZZ Pin for automatic power-down

• JEDEC-standard 119-bump BGA and 165-bump FPBGA

Rev: 1.00 1/2011

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Read-Write-Read bus utilization; fully pin-compatible with

both pipelined and flow through NtRAM™, NoBL™ and

ZBT™ SRAMs

packages

Flow Through

Pipeline

3-1-1-1

2-1-1-1

9Mb Pipelined and Flow Through

Synchronous NBT SRAM

Parameter Synopsis

1/33

Curr (x18)

Curr (x36)

Curr (x18)

Curr (x36)

tCycle

Functional Description

The GS882Z18/36C(B/D)-300M is a 9Mbit Synchronous

Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL

or other pipelined read/double late write or flow through read/

single late write SRAMs, allow utilization of all available bus

bandwidth by eliminating the need to insert deselect cycles

when the device is switched from read to write cycles.

Because it is a synchronous device, address, data inputs, and

read/write control inputs are captured on the rising edge of the

input clock. Burst order control (LBO) must be tied to a power

rail for proper operation. Asynchronous inputs include the

Sleep mode enable (ZZ) and Output Enable. Output Enable can

be used to override the synchronous control of the output

drivers and turn the RAM's output drivers off at any time.

Write cycles are internally self-timed and initiated by the rising

edge of the clock input. This feature eliminates complex off-

chip write pulse generation required by asynchronous SRAMs

and simplifies input signal timing.

The GS882Z18/36C(B/D)-300M may be configured by the

user to operate in Pipeline or Flow Through mode. Operating

as a pipelined synchronous device, in addition to the rising-

edge-triggered registers that capture input signals, the device

incorporates a rising edge triggered output register. For read

cycles, pipelined SRAM output data is temporarily stored by

the edge-triggered output register during the access cycle and

then released to the output drivers at the next rising edge of

clock.

The GS882Z18/36C(B/D)-300M is implemented with GSI's

high performance CMOS technology and is available in

JEDEC-standard 119-bump BGA and 165-bump FPBGA

packages.

-300M

280

315

220

245

2.5

3.3

5.0

Unit

GS882Z18/36CB-300M

GS882Z18/36CD-300M

2.5 V or 3.3 V V

2.5 V or 3.3 V I/O

300 MHz

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