CYIL1SM0300AA_09 CYPRESS [Cypress Semiconductor], CYIL1SM0300AA_09 Datasheet - Page 17

• Manufacturer Part Number: CYIL1SM0300AA_09
• Description: LUPA-300 CMOS Image Sensor
• Manufacturer: CYPRESS [Cypress Semiconductor]

Integration Timing
Integration Timing in Mastermode
In mastermode the integration time, the dual slope (DS)
integration time, and triple slope (TS) integration time are set by
the SPI settings.
relationship with the SPI registers. The timing concerning
integration is expressed in number of lines read out. The timing
is controlled by four SPI registers which need to be uploaded with
the desired number of lines. This number is then compared with
the line counter that keeps track of the number of lines that is
read out.
RES1_LENGTH <11:0>: The number of lines read out (minus 1)
after which the pixel reset drops and the integration starts.
Document Number: 001-00371 Rev. *F
RESET_N
READOUT
SAMPLE
RESET
# LINES
PIXEL
PIXEL
Figure 15
FOT
ROT
shows the integration timing and the
Integration frame I+1
1
Readout frame I
L1
K1
Res1_length
Figure 15. Integration Timing in Master Mode
Figure 14. Global Readout Timing
L2
K2
Res2_timer
Readout Pixels
Readout Lines
...
...
RES2_TIMER <11:0>: The number of lines read out (minus 1)
after which the dual slope reset pulse is given. The length of the
pulse is given by the formula: 4*(12*(GRAN<1:0>+1)+1) (in clock
cycles).
RES3_TIMER < 11:0>: The number of lines read out (minus 1)
after which the triple slope reset pulse is given. The length of the
pulse is given by the formula: 4*(12*(GRAN<1:0>+1)+1) (in clock
cycles).
FT_TIMER <11:0>: The number of lines read out (minus 1) after
which the Frame Transfer (FT) and the FOT starts. The length of
the pulse is given by the formula: 4*(12*(GRAN<1:0>+1)+1) (in
clock cycles).
Res3_timer
Integration frame I + 2
Readout frame I+1
L480
K160
FT_timer
FOT
1
CYIL1SM0300AA
Res1_length
Page 17 of 31
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