ZL50070GAC ZARLINK [Zarlink Semiconductor Inc], ZL50070GAC Datasheet - Page 12

• Manufacturer Part Number: ZL50070GAC
• Description: 24 K Channel Digital Switch with High Jitter Tolerance, Rate Conversion per Group of 4 Streams (8, 16, 32 or 64 Mbps), and 96 Inputs and 96 Outputs
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Pin Description (continued)
P20, V13, W13, Y13, AA16,
G20, G22, H19, H21, H22,
L20, M18, M19, M22, N19,
L22, M20, M21, N18, N20,
A18, B20, B22, C18, C21,
C22, D17, D20, E16, E19,
D21, D22, E18, E20, F14,
F18, F19, F21, G18, H17,
A21, B19, C20, D16, D19,
E21, E22, F20,F22, G19,
N21, N22, R3, R21, R22,
K18, K20, K21, L17, L21,
H18, H20, J18, J19, J22,
J20, J21, K22, L18, L19,
P21, P22, AB13, AB14
A1, AB4, R18, E14
G5, Y6, T19, C17
W15, V14
AA17
Pin
L1
CK_SEL0-1
CKo0-3
FPo0-3
Name
ODE
NC
IC
Zarlink Semiconductor Inc.
ST-BUS/GCI-Bus Clock Outputs (3.3 V Outputs with Slew-Rate
Control)
These clock outputs can be programmed to generate 8.192 MHz,
16.384 MHz, 32.678 MHz or 65.536 MHz TDM clock outputs. The
active edge can be programmed to be either rising or falling. The
source of the clock outputs can be derived from either the CKi2-0
inputs or the internal system clock. The frequency, active edge and
source of each clock output can be programmed independently by
the Output Clock Control Register (Section 14.6). For 65.536 MHz
output clock, the total loading on the output should not be
larger than 10pF
ST-BUS/GCI-Bus Frame Pulse Outputs (3.3 V Outputs with
Slew-Rate Control)
These 8 kHz output pulses mark the frame boundary of the TDM
data streams. The pulse width is nominally one clock period of the
corresponding CKo output. The active state of each frame pulse
may be either high or low, independently programmed by the
Output Clock Control Register (Section 14.6).
Master Clock Input Select (5 V Tolerant Inputs)
Inputs used to select the frequency and frame alignment of CKi0
and FPi0:
CK_SEL1 = 0, CK_SEL0 = 0, 8.192 MHz
CK_SEL1 = 0, CK_SEL0 = 1, 16.384 MHz
CK_SEL1 = 1, CK_SEL0 = 0, 32.768 MHz
CK_SEL1 = 1, CK_SEL0 = 1, 65.536 MHz
Output Drive Enable (5 V Tolerant Input with Internal Pull-up)
This is the asynchronous output enable control for the output
streams. When it is high, the streams are enabled. When it is low,
the output streams are tristated.
Internal Connections
In normal mode these pins MUST be connected low.
No Connection
In normal mode these pins MUST be left unconnected.
ZL50070
12
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Description
Data Sheet