ZL50070GAC ZARLINK [Zarlink Semiconductor Inc], ZL50070GAC Datasheet - Page 22

• Manufacturer Part Number: ZL50070GAC
• Description: 24 K Channel Digital Switch with High Jitter Tolerance, Rate Conversion per Group of 4 Streams (8, 16, 32 or 64 Mbps), and 96 Inputs and 96 Outputs
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

6.0
In Message Mode (MSG), microprocessor data can be broadcast to the output data streams on a per-channel
basis. This feature is useful for transferring control and status information to external circuits or other TDM devices.
For a given output channel, when the corresponding Per Channel Function (bits 31 - 29) in the Connection Memory
are set to Message Mode (010), the Connection Memory’s lowest data byte (bits 7 - 0) is output in the timeslot, in
the outgoing timeslot. Refer to Section 14.1.1, Connection Memory Bit Functions, for programming details
To increase programming bandwidth, the ZL50070 has separate addressable 32 bit memory locations, called
Connection Memory Least Significant Bytes (LSB), which provide direct access to the Connection Memories’
Lowest data bytes (bits 7 - 0). Up to four consecutive message mode channels can be set with one Connection
Memory LSB access. Refer to Section 14.1.2, Connection Memory LSB, for programming details.
6.1
All TDM input channels can be read via the microprocessor port. This feature is useful for receiving control and
status information from external circuits or other TDM devices. Each 32 bit Data Memory access enables up to four
consecutive input channels to be monitored. The Data Memory field is read only; any attempt to write to this
address range will result in a bus error condition signalled back to the host processor. Refer to Section 14.2, Data
Memory, for programming details.
The latency of data reads is up to 3 frames, depending on when the input timeslots are sampled.
6.2
See Section 14.7, Block Init Register, and Section 14.8, Block Init Enable Register, for programming details.
This feature allows for fast initialization of the connection memory after power up. When the block programming
mode is enabled, the contents of Block Init Register are written to all Connection Memory Bits. This operation
completes in one 125 µs frame. During Connection Memory initialization, all TDM output streams are set to high
impedance.
7.0
See Section 14.1.1, Connection Memory Bit Functions, for programming details.
The switching of information from the input serial streams to the output serial streams results in a throughput delay.
The device can be programmed to perform timeslot interchange functions with different throughput delay
capabilities on a per-channel basis. For voice applications, select variable throughput delay to ensure minimum
delay between input and output data. In wideband data application, select constant delay to maintain the frame
integrity of the information through the switch. The delay through the device varies according to the type of
throughput delay selected by programming the Per-Channel Function (bits 31 - 29) in the Connection Memories.
When these bits are set to 011, the channel is in variable delay mode. When they are set to 100, the channel is in
constant delay mode.
7.1
In this mode the frame integrity is maintained in all switching configurations. The delay though the switch is 2
frames - Input Channel + Output Channel. This can result in a minimum delay of 1 frame + 1 channel if the last
channel of a stream is switched to the first channel of a stream. The maximum delay is 1 channel short of 3 frames
delay. This occurs when the first channel of a stream is switched to the last channel of a stream.
The data throughput delay is expressed as a function of ST-BUS/GCI-Bus frames, input channel number (n) and
output channel number (m). The data throughput delay (T) is:
Data Memory Read
Connection Memory Block Programming
Constant Delay Mode
Message Mode
Data Delay Through the Switching Paths
T = 2 frames + (n - m)
Zarlink Semiconductor Inc.
ZL50070
22
Data Sheet