ZL50070GAC ZARLINK [Zarlink Semiconductor Inc], ZL50070GAC Datasheet - Page 13

• Manufacturer Part Number: ZL50070GAC
• Description: 24 K Channel Digital Switch with High Jitter Tolerance, Rate Conversion per Group of 4 Streams (8, 16, 32 or 64 Mbps), and 96 Inputs and 96 Outputs
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Pin Description (continued)
A8, C9, B8, E10, A7, A6, D9,
B10, C10, A9, D10, B9, F11,
E9, C8, A5, B6, C7, D8, E8,
A4, B5, C6, D7, F8, A3, B4
D13, B15, A15, B14, C13,
B16, A17, A16, C14, E13,
A14, B13, E12, D12, A13,
A11, C11, E11, B11, A10,
C12, D11, B12, A12
C16
D14
C15
D15
A19
B17
Pin
BERR
Name
D0-31
A0-18
WAIT
R/W
DTA
CS
DS
Microprocessor Port and Reset
Zarlink Semiconductor Inc.
Microprocessor Port Data Bus (5 V Tolerant Bi-directional with
Slew-Rate Output Control)
32 or 16 bit bidirectional data bus. Used for microprocessor access
to internal memories and registers. When 16 bit mode is selected
(D16B is logic 1), D31-16 are unused and must be connected to
defined logic levels.
Microprocessor Port Address Bus (5 V Tolerant Inputs)
19 bit address bus for the internal memories and registers. In 16 bit
bus mode (D16B is logic 1), please note A0 is not used and must
be connected to a defined logic level.
In Intel 32 bit mode: A1 = BE
Chip Select Input (5 V Tolerant Input)
Active low input used with DS to enable read and write access to
the ZL50070.
Data Strobe Input (5 V Tolerant Input)
Active low input used with CS to enable read and write access to
the ZL50070.
Read/Write Input (5 V Tolerant Input)
This input controls the direction of the data bus lines (D31 - 0)
during a microprocessor access. This pin is set high and low for the
read and write access respectively.
Data Transfer Acknowledge (5 V Tolerant, 3.3 V Tri-state
Output with Slew-Rate)
This active low output indicates that a data bus transfer is
complete. Usually used with a Motorola interface. An external
pull-up resistor is required to hold this pin HIGH when output is
high-impedance.
Transfer Bus Error Output with Slew Rate Control (5 V
Tolerant, 3.3 V Tri-state Outputs with Slew-Rate Control)
This pin goes low whenever the microprocessor attempts to access
an invalid memory space inside the device. In Motorola bus mode,
if this bus error signal is activated, the data transfer acknowledge
signal, DTA, will not be generated. In Intel bus mode, the
generation of the DTA is not affected by this BERR signal. An
external pull-up resistor is required to hold a HIGH level when
output is high-impedance.
Data Transfer Wait Output (5 V Tolerant, 3.3 V Tri-state Output
with Slew Rate)
Active low wait signal output. It indicates that a data bus transfer is
complete when it goes from low to high. Usually used with an Intel
interface. An external pull-up resistor is required to hold this pin
HIGH when output is high-impedance.
ZL50070
13
Description
3
, A0 = BE
2
Data Sheet