ZL50070GAC ZARLINK [Zarlink Semiconductor Inc], ZL50070GAC Datasheet - Page 29

• Manufacturer Part Number: ZL50070GAC
• Description: 24 K Channel Digital Switch with High Jitter Tolerance, Rate Conversion per Group of 4 Streams (8, 16, 32 or 64 Mbps), and 96 Inputs and 96 Outputs
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

10.4.2
The operation of the write cycle is illustrated in Figure .
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The microprocessor asserts the R/W control signal low, to signal a write cycle. It also drives the address A,
data transfer size, SIZ1 - 0, and chip select logic drives the CS signal active low to select the ZL50070
The microprocessor then drives the data bus, D31 - 0 (D15 - 0 in 16 bit Mode) with the data to be written,
and then drives the DS signal active low, to signal the start of the bus cycle. The DS signal is held low for the
duration of the bus cycle
WAIT is asserted active low
The ZL50070 transfers the data presented on the data bus pins into the indicated memory or register
location(s). If the address is to an unused area of the memory space, or to the data memory, no data is
transferred. The microprocessor port cannot write to the Data Memory
The ZL50070 then de-asserts WAIT, and asserts either DTA or BERR, depending on the validity of the data
transfer
When the microprocessor observes the active low state of the DTA or the BERR signal, or the low-to-high
transition of the WAIT signal, it terminates the bus cycle by driving the DS pin inactive high
When the ZL50070 sees the DS signal go inactive high, it removes the assertions on the DTA or BERR
signals by driving them inactive high
When the ZL50070 sees the CS signal go inactive high, it tri-states the DTA, BERR and WAIT signals.
However, if CS goes inactive high before DS goes inactive high, the DTA, BERR and WAIT signals are
driven inactive high before they are tri-stated
At the end of an Intel bus cycle, DTA is always driven low to indicate the end of the data transfer, regardless
of BERR
Address A,
Write Cycle
SIZ1 - 0
BERR
The cycle termination signals WAIT & DTA are provided for all bus configurations
WAIT
Data
R/W
DTA
CS
DS
Hi-Z
Hi-Z
Hi-Z
Figure 10 - Read Cycle Operation
Zarlink Semiconductor Inc.
ZL50070
29
Hi-Z
Hi-Z
Data Sheet