INT5130 ETC1 [List of Unclassifed Manufacturers], INT5130 Datasheet
INT5130
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INT5130 Summary of contents
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... General Description The INT5130 integrated powerline MAC/PHY transceiver providing No New Wires to any room, over any wire, at speeds Mbps. The INT5130 provides the ability to select between a complete Media Independent Interface (MII reduced General Purpose Serial Interface (GPSI) for interconnection to the external MAC controller ...
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... PROM interface. Providing this configuration and control information through a separate E allows the system designer to leverage standard Ethernet drivers. The INT5130 operates on both 2.5V and 3.3V supplies, offers 5V I/O tolerance, and is packaged in a 144-pin LQFP. Intellon offers a complete solution for powerline communication applications by providing the INT5130 in conjunction with the INT1000 Analog Conversion IC ...
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... INT5130 Integrated Powerline MAC/PHY Transceiver Technical Data Sheet Contents Features .......................................................................................................................................................... 1 Applications.................................................................................................................................................... 1 General Description........................................................................................................................................ 1 Functional Block Diagram.............................................................................................................................. 2 Contents ......................................................................................................................................................... 3 Pin I/O.............................................................................................................................................................. 4 Pin Descriptions by Group............................................................................................................................. 5 Pin Diagram .................................................................................................................................................... 9 Functional Description................................................................................................................................. 10 MII Data Interface with MDI Control .......................................................................................................... 11 MII Interface............................................................................................................................................ 11 MDI Control Interface............................................................................................................................. 17 MII Management Register Set ............................................................................................................... 18 GPSI Interface with SPI Control................................................................................................................ 21 GPSI Interface ...
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... INT5130 Integrated Powerline MAC/PHY Transceiver Technical Data Sheet Pin I/O Pin Pin Signal No. No. 1 VDD_C 37 2 VDD_C 38 3 VDD_IO 39 4 MII_TX3 40 5 VSS_C 41 6 MII_TX2 42 7 VDD_C 43 8 MII_TX1 44 9 VSS_IO 45 10 VSS_C 46 11 MII_TX0/ 47 GPSI_TXD 12 MII_TXEN/ 48 GPSI_TXEN 13 VDD_C 49 14 MII_TXCLK/ 50 GPSI_TXCLK ...
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... MII Transmit Clock The transmit clock outputs a continuous 25MHz clock to the external MAC. MII Transmit Enable This signal indicates to the INT5130 that valid data is present on the MII_TX[3:0] pins. MII Transmit Error MII_TX_ER is activated by the external host controller when an error condition is detected during packet transmission ...
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... This signal is driven false in GPSI mode. SPI Slave Data Out SPI data from the INT5130 to the external host. SPI Slave Data In SPI data from the external host to the INT5130. This pin is shared with the MDI_ADRSEL[1]. SPI Slave Clock Timing reference signal for SPI_SDI and SPI_SDO. ...
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... Receive Enable signal Analog/Digital I/O ADC and DAC Data. Multiplexed parallel interface to INT1000 Analog Conversion IC. AGC Gain Select Gain control driven by the INT5130 to set the AGC level. ADC Calibrate This pin must remain low during normal operation of the ADC pulsed high to request a calibration cycle ...
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... Address select used to compare against the upper two bits of the MDI Address. These pins share function with SPIS_CS_N and SPIS_SDI and should be pulled-up or down with external resistors to set the appropriate value which is read by the INT5130 during power up. Management Data Interface/Serial Peripheral Interface Slave Select. ...
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... INT5130 Integrated Powerline MAC/PHY Transceiver Technical Data Sheet TEST1 Input TEST2 Input NC --- Power Supplies VDD_C 2.5v VSS_C VDD_IO 3.3v VSS_IO VDD_Q 3.3v VSS_Q Pin Diagram 1 VDD_C 2 VDD_C 3 VDD_IO 4 MII_TX3 5 VSS_C 6 MII_TX2 7 VDD_C 8 MII_TX1 9 VSS_IO 10 VSS_C 11 MII_TX0/GPSI_TXD 12 MII_TXEN/GPSI_TXEN 13 VDD_C 14 MII_TXCLK/GPSI_TXCLK 15 VDD_Q 16 MII_TX_ER 17 VDD_C 18 MII_RX_ER/GPSI_RXD 19 VSS_C ...
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... INT5130 Integrated Powerline MAC/PHY Transceiver Technical Data Sheet Functional Description The interfaces that provide data, status, and control to and from the INT5130 include… External host interface provided via the Media Independent Interface (MII) format (described by IEEE802.3u, Clause 22 General Purpose Serial Interface (GPSI). ...
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... Data is transferred between the MAC and PHY over each 4-bit data path synchronous with a clock signal supplied to the host by the INT5130. The MII interface also provides a two wire bi- directional serial management data interface (MDI). This interface provides access to the status and control registers in the INT5130 ...
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... INT5130 Integrated Powerline MAC/PHY Transceiver Technical Data Sheet MII_TXCLK MII_CRS MII_TXEN MII_TXD[3:1], MII_TX0 MII_COL MII_RXCLK MII_CRS MII_RXDV MII_RXD[3:0] MII_CRS MII_TXEN MII_RXDV MII_COL Figure 5: MII TX With Collision Based On RX Activity INTELLON CONFIDENTIAL Rev 8.1 DATA DATA Figure 3: MII TX Waveform DATA DATA Figure 4: MII RX Waveform ...
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... INT5130 Integrated Powerline MAC/PHY Transceiver Technical Data Sheet MII_RX_ER, MII_COL, MII_CRS MII DC Characteristics Parameter Symbol Parameter Name Receive Timing MII_RX[3:0], MII_RXDV valid t MII_RVAL from MII_RXCLK Transmit Timing MII_TXEN, MII_TX0, MII_TX[3:1] t MII_TSU setup to MII_TXCLK MII_TXEN, MII_TX0, MII_TX[3:1] t MII_TH hold to MII_TXCLK INTELLON CONFIDENTIAL Rev 8 ...
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... MAC will be presented with expected preamble plus SFD. MII_CRS MII_CRS is used to tell the external host when the INT5130 is available for sending a packet. MII_CRS is asynchronous to MII_TXCLK. When a packet is being transmitted, CRS is held high. CRS will go low whenever the INT5130 is ready to accept another packet. ...
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... INT5130 Integrated Powerline MAC/PHY Transceiver Technical Data Sheet arbitrary amount of time, while the INT5130 is gaining access to the channel and transmitting the packet. MII_CRS does not affect the receive side of the channel. Once packets start arriving from the powerline medium and begin transmission to the external host controller over the MII interface, the external host MUST be ready to receive or the packet can be lost ...
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... Start Frame Delimiter Indicates the start of a frame and follows the preamble. The SFD bit sequence is 10101011. The start frame delimiter is stripped by the INT5130 when transmitting (the SFD is not transmitted on the PLC medium) and pre-pended by the INT5130 when receiving. INTELLON CONFIDENTIAL Rev 8 ...
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... Figure 10: Partition of Serial Bit Stream to Nibble Stream MDI Control Interface The Management Data Interface connects the external host to the INT5130 for purposes of controlling the INT5130 and gathering status. A specific frame format and protocol definition exists for exchanging management frames over this interface. A register definition exists as well that specifies a basic register set with an extension mechanism ...
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... INT5130 and the external host. Control information is driven by the external host synchronously with respect to MII_MDCLK and is sampled synchronously by the INT5130. Status information is transferred from the INT5130 to the external host in the same manner. Management Data Clock MII_MDCLK is sourced by the external host as the timing reference for transfer of information on the MII_MDIO signal ...
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... The turnaround time bit time spacing between the Register Address field and the Data field to avoid contention during a read transaction. For reads, both the external host and the INT5130 will remain in tri-state for the first bit time. The INT5130 will drive a “0” during the second bit time. ...
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... INT5130 Integrated Powerline MAC/PHY Transceiver Technical Data Sheet For writes, the external host will drive a “1” for the first bit time and a “0” bit for the second bit time. Data The data field is 16 bits. The first data bit transmitted and received shall be bit 15 of the register being addressed ...
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... GPSI is an interoperable interface providing a simple interconnection between the INT5130 and embedded microcontrollers. Data is transferred between the host controller and the INT5130 over separate 1-bit transmit and receive data paths synchronous with clock signals supplied to the host by the INT5130. GPSI Timing Diagrams The figures below show the transmission and reception of packets and the corresponding behavior of the GPSI interface ...
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... INT5130 Integrated Powerline MAC/PHY Transceiver Technical Data Sheet GPSI_TXEN GPSI_TXD GPSI_TXBSY Internal TX buffer available pulse GPSI_RXEN GPSI_RXD Internal RX buffer available pulse GPSI_COL GPSI_TXCLK GPSI_TXD GPSI_TXEN GPSI_TXBSY GPSI_COL GPSI_RXCLK GPSI_RXD GPSI_RXEN GPSI_COL INTELLON CONFIDENTIAL Rev 8 Case 1 Case 2 TX only RX Only Figure 15: GPSI Flow Control Diagram ...
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... GPSI_TXBSY: GPSI_TXBSY is an optionally used signal to tell the external host controller when the INT5130 is available for sending packets. When a packet is being transmitted, GPSI_TXBSY is held high. GPSI_TXBSY will go low whenever the INT5130 is ready to send another packet. If this signal is not used, the transmitting logic must pace the packet transmissions to ensure that no packets are lost due to buffer overflow ...
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... CRC). SPI Slave Interface The INT5130 implements a SPI Slave port that when connected to an external host controller containing a SPI Master, can be used to control access to the two configuration registers. The SPI Slave port uses a 16-bit control field (msb first) consisting of a 6-bit command field, a 5-bit reserved field, and a 5-bit address field to control access to the two configuration registers detailed above ...
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... SPIS_H Clocks The INT5130 runs from a single 100MHz oscillator input and generates a 50MHz clock to feed the ADC, a 50MHz clock to feed the DAC, the 25MHz MII clock, and the 10MHz GPSI clock. The 100MHz clock input directly feeds the clock distribution network that clocks up to 60% of the digital logic. Note: Both CLKIN and CLKOUT connect directly to the 2 ...
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... INT5130 Integrated Powerline MAC/PHY Transceiver Technical Data Sheet AFE Interface The INT5130 provides a simple parallel interface to the analog front end (AFE). The analog data is clocked into or out of the INT5130 on a 10-bit bi-directional parallel data bus under control of transmit or receive enable signals and sample clock references provided to the AFE from the INT5130. The INT5130 also provides a parallel byte-wide automatic gain control interface ...
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... INT5130 Integrated Powerline MAC/PHY Transceiver Technical Data Sheet DAC_CLK, ADC_CLK ADIO[9:0], RX_EN, TX_EN ADC_CLK ADIO[9:0] INTELLON CONFIDENTIAL Rev 8.1 t AFE_H 2.0V 1.5V 0. AFE_R AFE_FT t AFE_PW Figure 21: AFE Clock Waveforms DAC_CLK Figure 22: AFE Transmit Timing Diagram DATA Figure 23: AFE Receive Timing Diagram 27 t AFE_L ...
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... INT5130 Integrated Powerline MAC/PHY Transceiver Technical Data Sheet DAC DC Characteristics Symbol Parameter Number of Bits Data Format Sample Rate DAC DATA OUTPUTS V HIGH level output voltage OH V LOW level output voltage OL T Propagation Delay Time AFE_RVAL DAC CLOCK OUTPUT t DAC Clock Pulse Width ...
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... E PROM is intended to initialize the INT5130 with specific information that will not be changed throughout its normal course of operation. For specific features that require real-time control, such as those features found within the Set Transmit Characteristics MAC management frame, this information must be provided via the MAC ...
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... INT5130 Integrated Powerline MAC/PHY Transceiver Technical Data Sheet SPI Master Timing Diagram SPI_SCLK SPI_DI SPI_DO SPI_CS Figure 24: SPI Master Signal Timing Diagram SPI Master DC Characteristics Parameter Symbol t SPI_SCLK Frequency SPI_F t SPI_SCLK High Time SPI_HIGH t SPI_SCLK Low Time SPI_LOW t SPI_DI Valid Output Delay from SPI_SCLK ...
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... INT5130 Integrated Powerline MAC/PHY Transceiver Technical Data Sheet JTAG Port The JTAG port is implements the IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture. JTAG Timing Diagrams TCK Figure 25: JTAG (IEEE 1149.1) TCK Waveform INTELLON CONFIDENTIAL Rev 8.1 Table 14: LED Descriptions ...
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... INT5130 Integrated Powerline MAC/PHY Transceiver Technical Data Sheet TCK TDI, TMS TDO Output Signals Input Signals Figure 26: JTAG(IEEE 1149.1) Test Signal Timing JTAG DC Characteristics INTELLON CONFIDENTIAL Rev 8.1 t JTAG_SU t JTAG_H t JTAG_VD t t JTAG_OFD JTAG_OVD t JTAG_ISU t JTAG_IH 32 ADVANCE INFORMATION ...
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... INT5130 Integrated Powerline MAC/PHY Transceiver Technical Data Sheet Parameter Symbol Parameter Name t TCK Frequency JTAG_F t TCK Period JTAG_P t TCK High Time JTAG_H t TCK Low Time JTAG_L t TCK Rise Time JTAG_R t TCK Fall Time JTAG_FT t TDI, TMS Setup Time JTAG_SU t TDI, TMS Hold Time ...
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... INT5130 Integrated Powerline MAC/PHY Transceiver Technical Data Sheet Application Diagrams EEPROM LEDs MII 802.3 MAC PCI Controller for PCI MDI GPSI 802.3 MAC USB Controller for USB SPI GPSI Embedded IC with integrated USB 802.3 MAC SPI Controller INTELLON CONFIDENTIAL Rev 8.1 LEDs ...
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... Output HIGH Voltage V OH Output LOW voltage V OL Input Current I I Supply Current I DD Supply Current I CC Note: Any signal applied to the INT5130 clock pins, CLKIN and/or CLKOUT should not exceed 2.5 Volts. INTELLON CONFIDENTIAL Rev 8.1 Symbol Min Test Conditions Min 2 ...
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... INT5130 Integrated Powerline MAC/PHY Transceiver Technical Data Sheet Physical Dimensions .866 [22.00] .787 [20.00 .059 [1.50] INTELLON CONFIDENTIAL Rev 8.1 .866 [22.00] .787 [20.00] .020 [0.50] .009 [0.22] SEE DETAIL "A" .055 [1.40] Figure 30: Physical Dimensions 36 .004 [0.09] .024 [0.60] .039 [1.00] DETAIL "A" PACKAGE OUTLINE LQFP 144 LEAD DIMENSIONS NOMINAL ...
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... INT5130 Integrated Powerline MAC/PHY Transceiver Technical Data Sheet Ordering Information The INT5130 is available as part of the INT5130 Chipset, which includes both the INT5130 Integrated Powerline MAC/PHY Transceiver and the INT1000 Analog Conversion IC. Ordering information for the chipset is provided below. Catalog Part Number ...
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Intellon Corporation 5100 West Silver Springs Blvd. Ocala, FL 34482 (352) 237-7416 (352) 237-7616 (Fax) 2880 Lakeside Drive Suite #247 Santa Clara, CA 95054 (408) 567-1400 (408) 567-1401 www.intellon.com 2001 Intellon Corporation. Intellon Corporation reserves the right to make changes ...