INT5130 ETC1 [List of Unclassifed Manufacturers], INT5130 Datasheet - Page 10

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INT5130

Manufacturer Part Number
INT5130
Description
Integrated Powerline MAC/PHY Transceiver
Manufacturer
ETC1 [List of Unclassifed Manufacturers]
Datasheet

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Functional Description
The interfaces that provide data, status, and control to and from the INT5130 include…
INTELLON CONFIDENTIAL
Rev 8.1
TEST
E
External host interface provided via the Media Independent Interface (MII) format (described by
IEEE802.3u, Clause 22) or a General Purpose Serial Interface (GPSI).
Management control provided via the Management Data Interface (MDI) or the Serial Peripheral Interface
(SPI).
Analog Front End interface.
LEDs indicating network status.
Optional E
configuration information.
The JTAG port implements the IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture.
2
PROM
or SPI
MII or
GPSI
MDI
INT5130 Integrated Powerline MAC/PHY Transceiver Technical Data Sheet
2
PROM interface providing a path to initialize the INT5130 with PowerPacket-specific
Interface Block
MII/GPSII
Interface
Config
Master
Regs
JTAG
SPI
Interface
RISC uProcessor
LEDS
DMA
Figure 1: INT5130 Block Diagram
PowerPacket MAC
Core
ROM
Arbiter
Buffer
RAM
RAM
10
Sequencer
Link
DMA
PHY
FIFOs
PHY
Seq
PowerPacket PHY
PHY
Core
ADVANCE INFORMATION
Logic
AFE
ADIO(9:0)
AGC(7:0)

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