INT5130 ETC1 [List of Unclassifed Manufacturers], INT5130 Datasheet - Page 25

• Manufacturer Part Number: INT5130
• Description: Integrated Powerline MAC/PHY Transceiver
• Manufacturer: ETC1 [List of Unclassifed Manufacturers]

Clocks
The INT5130 runs from a single 100MHz oscillator input and generates a 50MHz clock to feed the ADC, a
50MHz clock to feed the DAC, the 25MHz MII clock, and the 10MHz GPSI clock. The 100MHz clock input
directly feeds the clock distribution network that clocks up to 60% of the digital logic. Note: Both CLKIN and
CLKOUT connect directly to the 2.5 V core of the IC and do not connect to the 3.3 V I/O ring. Therefore these
pins are not 3.3V or 5V tolerant.
The oscillator must have 25 PPM RMS maximum tolerance including initial accuracy, temperature/voltage
range and 5 years of aging. This oscillator must have a symmetry no worse than 40/60, jitter of 75 ps and 4 ns
rise and fall time. The oscillator must be rated over the desired temperature range and 10% voltage range.
The INT5130 uses a crystal input cell to receive the clock input.
INTELLON CONFIDENTIAL
Rev 8.1
SPI SlaveTiming Diagram
SPI Slave DC Characteristics
t
t
t
t
t
t
t
t
SPIS_F
SPIS_HIGH
SPIS_LOW
SPIS_SDOVD
SPIS_CSLEAD
SPIS_CSLAG
SPIS_SU
SPIS_H
Parameter
Symbol
INT5130 Integrated Powerline MAC/PHY Transceiver Technical Data Sheet
SPIS_SCLK
SPIS_SDI
SPIS_CS_N
SPIS_SDO
SPIS_SCLK Frequency
SPIS_SCLK High Time
SPIS_SCLK Low Time
SPIS_SDO Valid Output Delay from SPIS_SCLK
SPIS_CS Lead to SPIS_SCLK
SPIS_CS Lag from SPIS_SCLK
SPIS_SDI Setup Time to SPIS_SCLK
SPIS_SDI Hold Time to SPIS_SCLK
Parameter Name
Table 8: SPI Slave DC Characteristics
Figure 18: SPI Slave Signal Timing
25
MSB IN
MSB OUT
t
t
SPIS_SU
SPIS_CSLEAD
t
SPIS_H
t
@ 1.5 V
@ 1.5 V
@ 1.5 V
@ 1.5 V
@ 1.5 V
@ 1.5 V
@ 1.5 V
SPIS_SDOVD
Test Condition
BITS 6-1
BITS 6-1
t
SPIS_LOW
LSB IN
LSB OUT
1500
ADVANCE INFORMATION
Min
400
400
500
200
200
0
t
SPIS_HIGH
Max
500
2.1
t
SPIS_CSLAG
MHz
Unit
ns
ns
ns
ns
ns
ns
ns