CBTD3306D,112 NXP Semiconductors, CBTD3306D,112 Datasheet

IC FET BUS SWITCH 2BIT 8-SOIC

CBTD3306D,112

Manufacturer Part Number
CBTD3306D,112
Description
IC FET BUS SWITCH 2BIT 8-SOIC
Manufacturer
NXP Semiconductors
Series
74CBTDr
Type
FET Bus Switchr
Datasheet

Specifications of CBTD3306D,112

Circuit
1 x 1:1
Independent Circuits
2
Current - Output High, Low
15mA, 64mA
Voltage Supply Source
Single Supply
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
8-SOIC (3.9mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
935270513112
CBTD3306D
CBTD3306D
1. General description
2. Features and benefits
3. Ordering information
Table 1.
4. Marking
Table 2.
Type number
CBTD3306D
CBTD3306PW
CBTD3306GT
CBTD3306GM
Type number
CBTD3306D
CBTD3306PW
CBTD3306GT
CBTD3306GM
Ordering information
Marking codes
Package
Name
SO8
TSSOP8
XSON8
XQFN8U
The CBTD3306 dual FET bus switch features independent line switches. Each switch is
disabled when the associated output enable (nOE) input is HIGH.
The CBTD3306 is characterized for operation from −40 °C to +85 °C.
CBTD3306
Dual bus switch with level shifting
Rev. 04 — 25 March 2010
Designed to be used in 5 V to 3.3 V level shifting applications with internal diode
5 Ω switch connection between two ports
TTL-compatible input levels
Multiple package options
Latch-up protection exceeds 100 mA per JESD78B
ESD protection:
HBM JESD22-A114F exceeds 2000 V
CDM JESD22-C101E exceeds 1000 V
Description
plastic small outline package; 8 leads; body width 3.9 mm
plastic thin shrink small outline package; 8 leads;
body width 4.4 mm
plastic extremely thin small outline package; no leads; 8 terminals;
body 1 × 1.95 × 0.5 mm
plastic extremely thin quad flat package; no leads; 8 terminals;
body 1.6 × 1.6 × 0.5 mm
Marking code
W06
W06
W06
W06
Product data sheet
Version
SOT96-1
SOT530-1
SOT833-1
SOT902-1

Related parts for CBTD3306D,112

CBTD3306D,112 Summary of contents

Page 1

CBTD3306 Dual bus switch with level shifting Rev. 04 — 25 March 2010 1. General description The CBTD3306 dual FET bus switch features independent line switches. Each switch is disabled when the associated output enable (nOE) input is HIGH. The ...

Page 2

... NXP Semiconductors 5. Functional diagram Fig 1. Logic diagram 6. Pinning information 6.1 Pinning CBTD3306 1OE GND 4 001aak832 Fig 2. Pin configuration for SO8 (SOT96-1) CBTD3306 1OE GND 4 Transparent top view Fig 4. Pin configuration SOT833-1 (XSON8) CBTD3306_4 Product data sheet 1OE 2OE 2OE Fig 2OE ...

Page 3

... NXP Semiconductors 6.2 Pin description Table 3. Pin description Symbol Pin 1OE, 2OE GND Functional description [1] Table 4. Function selection Input nOE HIGH voltage level LOW voltage level high-impedance OFF-state. 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). ...

Page 4

... NXP Semiconductors 10. Static characteristics Table 7. Static characteristics Voltages are referenced to GND (ground = 0 V). Symbol Parameter V input clamping voltage IK I input leakage current I I supply current CC V pass voltage pass ΔI additional supply current CC C input capacitance I C off-state input/output io(off) capacitance ...

Page 5

... NXP Semiconductors 10.1 Typical pass voltage graphs 3.6 V pass (V) (1) 3.2 (2) (3) 2.8 (4) 2.4 2.0 4.4 4.8 = 100 μ ( Fig 6. Pass voltage versus supply voltage °C (typical) T amb 3.6 V pass (V) 3.2 2.8 2.4 2.0 4.4 4.8 = 100 μ (3) I =12 mA ...

Page 6

... NXP Semiconductors = 100 μ ( Fig 10. Pass voltage versus supply voltage; T CBTD3306_4 Product data sheet 3.6 V pass (V) 3.2 2.8 2.4 2.0 4.4 4.8 5.2 = −40 °C (typical) amb All information provided in this document is subject to legal disclaimers. Rev. 04 — 25 March 2010 CBTD3306 ...

Page 7

... NXP Semiconductors 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Symbol Parameter t propagation delay pd t enable time en t disable time dis [1] The propagation delay is the calculated RC time constant of the typical ON resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance) ...

Page 8

... NXP Semiconductors nOE input output LOW to OFF OFF to LOW output HIGH to OFF OFF to HIGH Measurement points are given in Logic levels: V and Fig 12. Enable and disable times Table 9. Measurement points Supply voltage Input 5.0 V ± 0 GND to 3 CBTD3306_4 Product data sheet GND ...

Page 9

... NXP Semiconductors 13. Test information Test data is given in Table All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz; Z The outputs are measured one at a time with one transition per measurement. Definitions for test circuit Load resistance Load capacitance including jig and probe capacitance. ...

Page 10

... NXP Semiconductors 14. Package outline SO8: plastic small outline package; 8 leads; body width 3 pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.069 0.01 0.004 0.049 Notes 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

Page 11

... NXP Semiconductors TSSOP8: plastic thin shrink small outline package; 8 leads; body width 4 pin 1 index 1 e DIMENSIONS (mm are the original dimensions UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.85 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...

Page 12

... NXP Semiconductors XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1. 8× (2) terminal 1 index area DIMENSIONS (mm are the original dimensions) ( UNIT b D max max 0.25 2.0 mm 0.5 0.04 0.17 1.9 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. ...

Page 13

... NXP Semiconductors XQFN8U: plastic extremely thin quad flat package; no leads; 8 terminals; UTLP based; body 1.6 x 1.6 x 0.5 mm terminal 1 index area metal area not for soldering 2 1 terminal 1 index area DIMENSIONS (mm are the original dimensions) A UNIT max 0.05 0.25 1.65 mm 0.5 0.00 ...

Page 14

... NXP Semiconductors 15. Abbreviations Table 11. Abbreviations Acronym Description CDM Charged Device Model ESD ElectroStatic Discharge FET Field Effect Transistor HBM Human Body Model PRR Pulse Rate Repetition TTL Transistor-Transistor Logic 16. Revision history Table 12. Revision history Document ID Release date CBTD3306_4 20100325 CBTD3306_3 20100223 • ...

Page 15

... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...

Page 16

... NXP Semiconductors 18. Contact information For more information, please visit: For sales office addresses, please send an email to: CBTD3306_4 Product data sheet http://www.nxp.com salesaddresses@nxp.com All information provided in this document is subject to legal disclaimers. Rev. 04 — 25 March 2010 CBTD3306 Dual bus switch with level shifting © ...

Page 17

... NXP Semiconductors 19. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Functional description . . . . . . . . . . . . . . . . . . . 3 8 Limiting values Recommended operating conditions Static characteristics 10.1 Typical pass voltage graphs . . . . . . . . . . . . . . . 5 11 Dynamic characteristics ...

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