GS8182Q36BD-200I GSI Technology, GS8182Q36BD-200I Datasheet

GS8182Q36BD-200I

Manufacturer Part Number

GS8182Q36BD-200I

Description

Manufacturer

GSI Technology

Datasheet

1.GS8182Q18BD-133I.pdf (36 pages)

Specifications of GS8182Q36BD-200I

Lead_time

2 weeks

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Part Number

Manufacturer

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Price

Company:

H&T Electronics

Part Number:

GS8182Q36BD-200I

Quantity:

159

Current page: 1 of 36
Download datasheet (2Mb)

165-Bump BGA

Commercial Temp

Industrial Temp

Features

• Simultaneous Read and Write SigmaQuad™ Interface

• JEDEC-standard pinout and package

• Dual Double Data Rate interface

• Byte Write controls sampled at data-in time

• Burst of 2 Read and Write

• 1.8 V +100/–100 mV core power supply

• 1.5 V or 1.8 V HSTL Interface

• Pipelined read operation

• Fully coherent read and write pipelines

• ZQ pin for programmable output drive strength

• IEEE 1149.1 JTAG-compliant Boundary Scan

• Pin-compatible with present 9Mb and future 36Mb and

• 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package

• RoHS-compliant 165-bump BGA package available

SigmaQuad™ Family Overview

The GS8182Q08/09/18/36BD are built in compliance with

the SigmaQuad-II SRAM pinout standard for Separate I/O

synchronous SRAMs. They are 18,874,368-bit (18Mb)

SRAMs. The GS8182Q08/09/18/36BD SigmaQuad SRAMs

are just one element in a family of low power, low voltage

HSTL I/O SRAMs designed to operate at the speeds needed to

implement economical high performance networking systems.

Clocking and Addressing Schemes

The GS8182Q08/09/18/36BD SigmaQuad-II SRAMs are

synchronous devices. They employ two input register clock

inputs, K and K. K and K are independent single-ended clock

inputs, not differential inputs to a single differential clock input

buffer. The device also allows the user to manipulate the

output register clock inputs quasi independently with the C and

Rev: 1.03 1/2009

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

144Mb devices

tKHQV

tKHKH

0.45 ns

3.0ns

-333

0.45 ns

3.3 ns

-300

Parameter Synopsis

1/36

18Mb SigmaQuad-II

Burst of 2 SRAM

0.45 ns

4.0 ns

-250

GS8182Q08/09/18/36BD-333/300/250/200/167/133

C clock inputs. C and C are also independent single-ended

clock inputs, not differential inputs. If the C clocks are tied

high, the K clocks are routed internally to fire the output

registers instead.

Because Separate I/O SigmaQuad-II B2 RAMs always transfer

data in two packets, A0 is internally set to 0 for the first read or

write transfer, and automatically incremented by 1 for the next

transfer. Because the LSB is tied off internally, the address

field of a SigmaQuad-II B2 RAM is always one address pin

less than the advertised index depth (e.g., the 1M x 18 has a

512K addressable index).

0.45 ns

5.0 ns

-200

1 mm Bump Pitch, 11 x 15 Bump Array

165-Bump, 13 mm x 15 mm BGA

6.0 ns

0.5 ns

-167

Bottom View

7.5 ns

0.5 ns

-133

1.8 V and 1.5 V I/O

333 MHz–133 MHz

1.8 V V

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