GS8342T18AE-250I GSI Technology, GS8342T18AE-250I Datasheet

GS8342T18AE-250I

Manufacturer Part Number

GS8342T18AE-250I

Description

Manufacturer

GSI Technology

Datasheet

1.GS8342T18AE-167I.pdf (37 pages)

Specifications of GS8342T18AE-250I

Lead_time

2 weeks

Current page: 1 of 37
Download datasheet (2Mb)

165-Bump BGA

Commercial Temp

Industrial Temp

Features

• Simultaneous Read and Write SigmaCIO™ Interface

• Common I/O bus

• JEDEC-standard pinout and package

• Double Data Rate interface

• Byte Write (x36, x18, and x9) and Nybble Write (x8) function

• Burst of 2 Read and Write

• 1.8 V +100/–100 mV core power supply

• 1.5 V or 1.8 V HSTL Interface

• Pipelined read operation with self-timed Late Write

• Fully coherent read and write pipelines

• ZQ pin for programmable output drive strength

• IEEE 1149.1 JTAG-compliant Boundary Scan

• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package

• RoHS-compliant 165-bump BGA package available

• Pin-compatible with present 9Mb and 18Mb and future 72Mb

SigmaCIO™ Family Overview

The GS8342T08/09/18/36AE are built in compliance with the

SigmaCIO DDR-II SRAM pinout standard for Common I/O

synchronous SRAMs. They are 37,748,736-bit (36Mb)

SRAMs. The GS8342T08/09/18/36AE SigmaCIO SRAMs are

just one element in a family of low power, low voltage HSTL

I/O SRAMs designed to operate at the speeds needed to

implement economical high performance networking systems.

Clocking and Addressing Schemes

The GS8342T08/09/18/36AE SigmaCIO DDR-II SRAMs are

synchronous devices. They employ two input register clock

inputs, K and K. K and K are independent single-ended clock

inputs, not differential inputs to a single differential clock input

buffer. The device also allows the user to manipulate the

output register clock inputs quasi independently with the C and

C clock inputs. C and C are also independent single-ended

Rev: 1.05 12/2007

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

and 144Mb devices

tKHKH

tKHQV

0.45 ns

3.0 ns

-333

Parameter Synopsis

36Mb SigmaCIO DDR-II

1/37

0.45 ns

3.3 ns

-300

Burst of 2 SRAM

clock inputs, not differential inputs. If the C clocks are tied

high, the K clocks are routed internally to fire the output

registers instead.

Common I/O x36 and x18 SigmaCIO DDR-II B2 RAMs

always transfer data in two packets. When a new address is

loaded, A0 presets an internal 1 bit address counter. The

counter increments by 1 (toggles) for each beat of a burst of

two data transfer.

Common I/O x8 SigmaCIO DDR-II B2 RAMs always transfer

data in two packets. When a new address is loaded, the LSB

is internally set to 0 for the first read or write transfer, and

incremented by 1 for the next transfer. Because the LSB is

tied off internally, the address field of a x8 SigmaCIO DDR-II

B4 RAM is always one address pin less than the advertised

index depth (e.g., the 8M x 8 has a 2M addressable index).

0.45 ns

4.0 ns

-250

GS8342T08/09/18/36AE-333/300/250/200/167

0.45 ns

1 mm Bump Pitch, 11 x 15 Bump Array

5.0 ns

-200

165-Bump, 15 mm x 17 mm BGA

6.0 ns

0.5 ns

Bottom View

-167

1.8 V and 1.5 V I/O

167 MHz–333 MHz

1.8 V V

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