GS88018BT-300I GSI [GSI Technology], GS88018BT-300I Datasheet
GS88018BT-300I
Related parts for GS88018BT-300I
GS88018BT-300I Summary of contents
Page 1
... Pb-Free 100-lead TQFP package available Functional Description Applications The GS88018/32/36BT is a 9,437,184-bit (8,388,608-bit for x32 version) high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support ...
Page 2
DDQ ...
Page 3
DDQ ...
Page 4
DQP DDQ ...
Page 5
TQFP Pin Description Symbol Type I — ...
Page 6
Register – LBO ADV CK ADSC ADSP Power Down ZZ Control Note: Only x36 version shown ...
Page 7
Mode Pin Functions Mode Name Burst Order Control Output Register Control Power Down Control FLXDrive Output Impedance Control Note: There is a pull-up device onthe FT pin and a pull-down device on the ZZ pin, so those this input pins ...
Page 8
Byte Write Truth Table Function GW Read H Read H Write byte a H Write byte b H Write byte c H Write byte d H Write all bytes H Write all bytes L Notes: 1. All byte outputs are ...
Page 9
Synchronous Truth Table Address Operation Used Deselect Cycle, Power Down Deselect Cycle, Power Down Deselect Cycle, Power Down Read Cycle, Begin Burst External Read Cycle, Begin Burst External Write Cycle, Begin Burst External Read Cycle, Continue Burst Read Cycle, Continue ...
Page 10
Notes: 1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low. 2. The upper portion of the diagram assumes active use of only the Enable (E1) and Write (B that ADSP is tied ...
Page 11
Notes: 1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from Read cycles ...
Page 12
Absolute Maximum Ratings (All voltages reference Symbol DDQ V I/O V Voltage on Other Input Pins IN I Input Current on Any Pin IN I Output Current on Any I/O Pin OUT P ...
Page 13
V Range Logic Levels DDQ3 Parameter V Input High Voltage DD V Input Low Voltage DD V I/O Input High Voltage DDQ V I/O Input Low Voltage DDQ Notes: 1. The part numbers of Industrial Temperature Range versions end the ...
Page 14
Undershoot Measurement and Timing 50% V – 2 50% tKC Capacitance 2 Parameter Input Capacitance Input/Output Capacitance Note: ...
Page 15
DC Electrical Characteristics Parameter Input Leakage Current (except mode pins) ZZ Input Current FT, SCD, ZQ Input Current Output Leakage Current Output High Voltage Output High Voltage Output Low Voltage Rev: 1.04 2/2005 Specifications cited are subject to change without ...
Page 16
Operating Currents Parameter Test Conditions (x32/ x36) Device Selected; All other inputs Operating ≥V or ≤ V Current IH IL Output open (x18) Standby ZZ ≥ V – 0.2 V — DD Current Device Deselected; Deselect All other inputs — ...
Page 17
AC Electrical Characteristics Parameter Clock Cycle Time Clock to Output Valid Clock to Output Invalid Pipeline Clock to Output in Low-Z Setup time Hold time Clock Cycle Time Clock to Output Valid Clock to Output Invalid Flow Through Clock to ...
Page 18
Begin Read A Cont Single Read Single Read CK ADSP tS tH ADSC tS ADV tS tH A0– Ba– tOE DQa–DQd Rev: 1.04 2/2005 Specifications cited ...
Page 19
Begin Read A Cont tKH tKH CK ADSP tS tH ADSC tS tH ADV tS tH A0– Ba– and E3 only sampled with ADSC tOE ...
Page 20
... During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates normally after ZZ recovery time. ...
Page 21
TQFP Package Drawing (Package T) Symbol Description Min. Nom. Max A1 Standoff 0.05 A2 Body Thickness 1.35 b Lead Width 0.20 c Lead Thickness 0.09 D Terminal Dimension 21.9 D1 Package Body 19.9 E Terminal Dimension 15.9 E1 Package Body ...
Page 22
... GS88036BT-333 256K x 36 GS88036BT-300 256K x 36 GS88036BT-250 256K x 36 GS88036BT-200 256K x 36 GS88036BT-150 512K x 18 GS88018BT-333I 512K x 18 GS88018BT-300I 512K x 18 GS88018BT-250I 512K x 18 GS88018BT-200I 512K x 18 GS88018BT-150I 256K x 32 GS88032BT-333I 256K x 32 GS88032BT-300I 256K x 32 GS88032BT-250I 256K x 32 ...
Page 23
... GS88036BGT-150I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS88018BT-150IT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow through mode-selectable by the user ...
Page 24
... Sync SRAM Datasheet Revision History DS/DateRev. Code: Old; Types of Changes New Format or Content 88018B_r1 88018B_r1; 88018B_r1_01 88018B_r1_01; 88018B_r1_02 88018B_r1_02; 88018B_r1_03 88018B_r1_03; 88018B_r1_04 Rev: 1.04 2/2005 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. • Creation of new datasheet • ...