GS864036GT-167V GSI [GSI Technology], GS864036GT-167V Datasheet
GS864036GT-167V
Related parts for GS864036GT-167V
GS864036GT-167V Summary of contents
Page 1
... RoHS-compliant 100-lead TQFP package available Functional Description Applications The GS864018/32/36T-xxxV is a 75,497,472-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support ...
Page 2
GS864018T-xxxV 100-Pin TQFP Pinout (Package T) 100 DDQ ...
Page 3
GS864032T-xxxV 100-Pin TQFP Pinout (Package T) 100 DDQ ...
Page 4
GS864036T-xxxV 100-Pin TQFP Pinout (Package T) 100 DQP DDQ V 5 ...
Page 5
TQFP Pin Description Symbol Type I ...
Page 6
Register – LBO ADV CK ADSC ADSP Power Down ZZ Control Note: Only x36 version shown ...
Page 7
Mode Pin Functions Mode Name Burst Order Control Output Register Control Power Down Control Note: There is a pull-up device on the FT pin and a pull-down device on the ZZ pin, so this input pin can be unconnected and ...
Page 8
Byte Write Truth Table Function GW Read H Read H Write byte a H Write byte b H Write byte c H Write byte d H Write all bytes H Write all bytes L Notes: 1. All byte outputs are ...
Page 9
Synchronous Truth Table Address Operation Used Deselect Cycle, Power Down Deselect Cycle, Power Down Deselect Cycle, Power Down Read Cycle, Begin Burst External Read Cycle, Begin Burst External Write Cycle, Begin Burst External Read Cycle, Continue Burst Read Cycle, Continue ...
Page 10
Notes: 1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low. 2. The upper portion of the diagram assumes active use of only the Enable (E1, E2, and E3) and Write (B control ...
Page 11
Notes: 1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from Read cycles ...
Page 12
Absolute Maximum Ratings (All voltages reference Symbol Voltage on V DDQ V I/O V Voltage on Other Input Pins IN I Input Current on Any Pin IN I Output Current on Any I/O ...
Page 13
V & V Range Logic Levels DDQ2 DDQ1 Parameter V Input High Voltage DD V Input Low Voltage DD Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica- tions ...
Page 14
AC Test Conditions Parameter Input high level Input low level Input slew rate Input reference level Output reference level Output load Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. ...
Page 15
Operating Currents Parameter Test Conditions Device Selected; All other inputs Operating ≥V or ≤ V Current IH IL Output open Standby ZZ ≥ V – 0 Current Device Deselected; Deselect All other inputs Current ≥ ≤ ...
Page 16
AC Electrical Characteristics Parameter Clock Cycle Time Clock to Output Valid Clock to Output Invalid Pipeline Clock to Output in Low-Z Setup time Hold time Clock Cycle Time Clock to Output Valid Clock to Output Invalid Flow Through Clock to ...
Page 17
Begin Read A Cont Single Read Single Read CK ADSP tS tH ADSC tS ADV tS tH A0– Ba– tOE DQa–DQd Rev: 1.01 6/2006 Specifications cited ...
Page 18
Begin Read A Cont tKH tKH CK ADSP tS tH ADSC tS tH ADV tS tH A0– Ba– and E3 only sampled with ADSC tOE ...
Page 19
... During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates normally after 2 cycles of wake up time. ...
Page 20
TQFP Package Drawing (Package T) Symbol Description Min. Nom. Max A1 Standoff 0.05 A2 Body Thickness 1.35 b Lead Width 0.20 c Lead Thickness 0.09 D Terminal Dimension 21.9 D1 Package Body 19.9 E Terminal Dimension 15.9 E1 Package Body ...
Page 21
... GS864032GT-167V Synchronous Burst GS864036GT-250V Synchronous Burst GS864036GT-200V Synchronous Burst GS864036GT-167V Synchronous Burst GS864018GT-250IV Synchronous Burst GS864018GT-200IV Synchronous Burst Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS864018T-300IVT. ...
Page 22
... GS864036GT-250IV Synchronous Burst GS864036GT-200IV Synchronous Burst GS864036GT-167IV Synchronous Burst Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS864018T-300IVT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user ...
Page 23
... Sync SRAM Datasheet Revision History DS/DateRev. Code: Old; Types of Changes New Format or Content 8640Vxx_r1 8640Vxx_r1; 8640xx_V_r_01 Rev: 1.01 6/2006 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. • Creation of new datasheet • Updated entire document to reflect new part nomenclature Content • ...