GS8320E18T-150 GSI [GSI Technology], GS8320E18T-150 Datasheet
GS8320E18T-150
Related parts for GS8320E18T-150
GS8320E18T-150 Summary of contents
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... RoHS-compliant 100-lead TQFP package available Functional Description Applications The GS8320E18/32/36T-xxxV is a 37,748,736-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support ...
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... DDQ Rev: 1.03 6/2006 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8320E18T-xxxV 100-Pin TQFP Pinout Top View 2/24 Preliminary GS8320E18/32/36T-xxxV ...
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DDQ ...
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DQP DDQ ...
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TQFP Pin Description Symbol Type I ...
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Register – LBO ADV CK ADSC ADSP Power Down ZZ Control Note: Only x36 version shown ...
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Mode Pin Functions Mode Name Burst Order Control Output Register Control Power Down Control Note: There is a pull-up device on the FT pin and a pull-down device on the ZZ pin, so this input pin can be unconnected and ...
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Byte Write Truth Table Function GW Read H Read H Write byte a H Write byte b H Write byte c H Write byte d H Write all bytes H Write all bytes L Notes: 1. All byte outputs are ...
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Synchronous Truth Table Address Operation Used Deselect Cycle, Power Down Deselect Cycle, Power Down Deselect Cycle, Power Down Read Cycle, Begin Burst External Read Cycle, Begin Burst External Write Cycle, Begin Burst External Read Cycle, Continue Burst Read Cycle, Continue ...
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Notes: 1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low. 2. The upper portion of the diagram assumes active use of only the Enable (E1) and Write (B that ADSP is tied ...
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Notes: 1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from Read cycles ...
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Absolute Maximum Ratings (All voltages reference Symbol Voltage on V DDQ V I/O V Voltage on Other Input Pins IN I Input Current on Any Pin IN I Output Current on Any I/O ...
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V & V Range Logic Levels DDQ2 DDQ1 Parameter V Input High Voltage DD V Input Low Voltage DD Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica- tions ...
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AC Test Conditions Parameter Input high level Input low level Input slew rate Input reference level Output reference level Output load Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. ...
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Rev: 1.03 6/2006 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. 15/24 Preliminary GS8320E18/32/36T-xxxV © 2001, GSI Technology ...
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AC Electrical Characteristics Parameter Symbol Clock Cycle Time Clock to Output Valid Clock to Output Invalid Pipeline Clock to Output in Low-Z Setup time Hold time Clock Cycle Time Clock to Output Valid Clock to Output Invalid Flow Through Clock ...
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Begin Read A Cont CK ADSP tS tH ADSC tS ADV tS tH Ao– Ba– tOE DQa–DQd Hi-Z Rev: 1.03 6/2006 Specifications cited are subject ...
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Begin Read A Cont tKH tKH CK ADSP tS tH ADSC tH tS ADV tS tH Ao– Ba– and E3 only sampled with ADSP and ADSC ...
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... During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates normally after 2 cycles of wake up time. ...
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TQFP Package Drawing (Package T) Symbol Description Min. Nom. Max A1 Standoff 0.05 A2 Body Thickness 1.35 b Lead Width 0.20 c Lead Thickness 0.09 D Terminal Dimension 21.9 D1 Package Body 19.9 E Terminal Dimension 15.9 E1 Package Body ...
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... DCD Synchronous Burst Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8320E18T-150IVT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user ...
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... DCD Synchronous Burst Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8320E18T-150IVT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user ...
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... DCD Synchronous Burst Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8320E18T-150IVT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user ...
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... Sync SRAM Datasheet Revision History DS/DateRev. Code: Old; Types of Changes New Format or Content 8320EV18_r1 8320EV18_r1; 8320EV18_r1_01 8320EV18_r1_01; 8320EV18_r1_02 8320EV18_r1_02; 8320Exx_V_r1_03 Rev: 1.03 6/2006 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. • Creation of new datasheet • Updated format Content/Format • ...