GS864218B-167IV GSI [GSI Technology], GS864218B-167IV Datasheet
GS864218B-167IV
Related parts for GS864218B-167IV
GS864218B-167IV Summary of contents
Page 1
... DCD RAMs hold the deselect command for one full cycle and then begin turning off their outputs just after the second rising edge of clock. The user may configure this SRAM for either mode of operation using the SCD mode input. Byte Write and Global Write ...
Page 2
BGA—x72 Common I/O—Top View (Package DQP DQP G ...
Page 3
GS864272C-xxxV 209-Bump BGA Pin Description Symbol Type I ...
Page 4
GS864272C-xxxV 209-Bump BGA Pin Description (Continued) Symbol Type DDQ Rev: 1.03 6/2006 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Description Core power supply I/O and Core ...
Page 5
BGA—x36 Common I/O—Top View DDQ DDQ DDQ DDQ ...
Page 6
BGA—x18 Common I/O—Top View DDQ DDQ DDQ DDQ ...
Page 7
GS864218/36B-xxxV 119-Bump BGA Pin Description Symbol Type I — ...
Page 8
Register – LBO ADV CK ADSC ADSP Power Down ZZ Control Note: Only x36 version shown ...
Page 9
Mode Pin Functions Mode Name Burst Order Control Output Register Control Power Down Control Single/Dual Cycle Deselect Control FLXDrive Output Impedance Control Note: There are pull-up devices on the ZQ, SCD, and FT pins and a pull-down device on the ...
Page 10
Byte Write Truth Table Function GW Read H Read H Write byte a H Write byte b H Write byte c H Write byte d H Write all bytes H Write all bytes L Notes: 1. All byte outputs are ...
Page 11
Synchronous Truth Table Address Operation Used Deselect Cycle, Power Down Deselect Cycle, Power Down Deselect Cycle, Power Down Read Cycle, Begin Burst External Read Cycle, Begin Burst External Write Cycle, Begin Burst External Read Cycle, Continue Burst Read Cycle, Continue ...
Page 12
Notes: 1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low. 2. The upper portion of the diagram assumes active use of only the Enable (E1) and Write (B that ADSP is tied ...
Page 13
Notes: 1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from read cycles ...
Page 14
Absolute Maximum Ratings (All voltages reference Symbol Voltage on V DDQ V I/O V Voltage on Other Input Pins IN I Input Current on Any Pin IN I Output Current on Any I/O ...
Page 15
V & V Range Logic Levels DDQ2 DDQ1 Parameter V Input High Voltage DD V Input Low Voltage DD Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica- tions ...
Page 16
AC Test Conditions Parameter Input high level Input low level Input slew rate Input reference level Output reference level Output load Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. ...
Page 17
Operating Currents Parameter Test Conditions Device Selected; All other inputs Operating ≥V or ≤ V Current IH IL Output open Standby ZZ ≥ V – 0 Current Device Deselected; Deselect All other inputs Current ≥ ≤ ...
Page 18
AC Electrical Characteristics Parameter Clock Cycle Time Clock to Output Valid Clock to Output Invalid Pipeline Clock to Output in Low-Z Setup time Hold time Clock Cycle Time Clock to Output Valid Clock to Output Invalid Flow Through Clock to ...
Page 19
Begin Read A Cont Single Read Single Read CK ADSP tS tH ADSC tS ADV tS tH A0– Ba– tOE DQa–DQd Rev: 1.03 6/2006 Specifications cited ...
Page 20
Begin Read A Cont tKH tKH CK ADSP tS tH ADSC tS tH ADV tS tH A0– Ba– and E3 only sampled with ADSC tOE ...
Page 21
Begin Read A Cont CK ADSP tS tH ADSC tS ADV tS tH Ao– Ba– tOE DQa–DQd Hi-Z Rev: 1.03 6/2006 Specifications cited are subject ...
Page 22
Begin Read A Cont tKH tKH CK ADSP tS tH ADSC tH tS ADV tS tH Ao– Ba– and E3 only sampled with ADSP and ADSC ...
Page 23
... During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates normally after ZZ recovery time. ...
Page 24
JTAG Pin Descriptions Pin Pin Name I/O Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate TCK Test Clock In from the falling edge of TCK. The TMS input is sampled ...
Page 25
TDI TMS TCK Identification (ID) Register The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in Capture-DR state with the IDCODE command loaded ...
Page 26
Tap Controller Instruction Set Overview There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific (Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be implemented in ...
Page 27
SAMPLE/PRELOAD SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and I/O buffers into ...
Page 28
JTAG TAP Instruction Set Summary Instruction Code EXTEST 000 Places the Boundary Scan Register between TDI and TDO. IDCODE 001 Preloads ID Register and places it between TDI and TDO. Captures I/O ring contents. Places the Boundary Scan Register between ...
Page 29
JTAG Port Recommended Operating Conditions and DC Characteristics (1.8/2.5 V Version) Parameter 1.8 V Test Port Input Low Voltage 2.5 V Test Port Input Low Voltage 1.8 V Test Port Input High Voltage 2.5 V Test Port Input High Voltage ...
Page 30
... TCK TDI TMS TDO Parallel SRAM input JTAG Port AC Electrical Characteristics Parameter Symbol TCK Cycle Time tTKC TCK Low to TDO Valid tTKQ TCK High Pulse Width tTKH TCK Low Pulse Width tTKL TDI & TMS Set Up Time tTS TDI & TMS Hold Time ...
Page 31
Body, 1.0 mm Bump Pitch Bump Array A aaa e Symbol Min Typ A — — A1 0.40 0.50 ∅b 0.50 0.60 c 0.31 0.36 D 21.9 22.0 Rev 1.0 Rev: 1.03 ...
Page 32
Package Dimensions—119-Bump FPBGA (Package B, Variation 2 A1 TOP VIEW SEATING PLANE C Rev: 1.03 6/2006 ...
Page 33
... GS864236GB-200V Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS864218B-167IVB. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user ...
Page 34
... GS864272GC-167IV Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS864218B-167IVB. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user ...
Page 35
... Sync SRAM Data Sheet Revision History DS/DateRev. Code: Old; New 8642Vxx_r1 8642Vxx_r1; 8642Vxx_r1_01 8642Vxx_r1_01; 8642Vxx_r1_02 8642Vxx_r1; 8642xx_V_r_01 Rev: 1.03 6/2006 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Types of Changes Format or Content • Creation of new datasheet • ...