GS880F18AT GSI [GSI Technology], GS880F18AT Datasheet

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GS880F18AT

Manufacturer Part Number
GS880F18AT
Description
512K x 18, 256K x 32, 256K x 36 8Mb Sync Burst SRAMs
Manufacturer
GSI [GSI Technology]
Datasheet
100-Pin TQFP
Commercial Temp
Industrial Temp
Features
• Flow Through mode operation; Pin 14 = No Connect
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 100-lead TQFP package
Functional Description
Applications
The GS880F18/32/36AT is a 9,437,184-bit (8,388,608-bit for
x32 version) high performance synchronous SRAM with a
2-bit burst address counter. Although of a type originally
developed for Level 2 Cache applications supporting high
performance CPUs, the device now finds application in
synchronous SRAM applications, ranging from DSP main
store to networking chip set support.
Controls
Addresses, data I/Os, chip enables (E1, E2, E3), address burst
control inputs (ADSP, ADSC, ADV), and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
Rev: 1.03 11/2004
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Flow Through
2-1-1-1
9Mb Synchronous Burst SRAMs
512K x 18, 256K x 32, 256K x 36
Curr
Curr
tCycle
t
(x32/x36)
KQ
(x18)
Parameter Synopsis
1/23
-250
175
200
5.5
5.5
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
Designing for Compatibility
The JEDEC standard for Burst RAMS calls for a FT mode pin
option on Pin 14. Board sites for flow through Burst RAMS
should be designed with V
to ensure the broadest access to multiple vendor sources.
Boards designed with FT pin pads tied low may be stuffed with
GSI’s pipeline/flow through-configurable Burst RAMs or any
vendor’s flow through or configurable Burst SRAM. Boards
designed with the FT pin location tied high or floating must
employ a non-configurable flow through Burst RAM, like this
RAM, to achieve flow through functionality.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS880F18/32/36AT operates on a 2.5 V or 3.3 V power
supply. All input are 3.3 V and 2.5 V compatible. Separate
output power (V
from the internal circuits and are 3.3 V and 2.5 V compatible.
-225
165
190
6.0
6.0
-200
160
180
6.5
6.5
GS880F18/32/36AT-5.5/6/6.5/7/7.5/8.5
DDQ
-166
150
170
7.0
7.0
) pins are used to decouple output noise
-150
145
165
7.5
7.5
SS
connected to the FT pin location
-133
135
150
8.5
8.5
Unit
© 2001, GSI Technology
mA
mA
ns
ns
2.5 V or 3.3 V V
2.5 V or 3.3 V I/O
5.5 ns–8.5 ns
DD

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GS880F18AT Summary of contents

Page 1

... Boards designed with FT pin pads tied low may be stuffed with GSI’s pipeline/flow through-configurable Burst RAMs or any vendor’s flow through or configurable Burst SRAM. Boards designed with the FT pin location tied high or floating must employ a non-configurable flow through Burst RAM, like this RAM, to achieve flow through functionality ...

Page 2

DDQ ...

Page 3

DDQ ...

Page 4

DQP DDQ ...

Page 5

TQFP Pin Description Symbol Type I — ...

Page 6

Register – LBO ADV CK ADSC ADSP Power Down ZZ Control Note: Only x36 version shown ...

Page 7

Mode Pin Functions Mode Name Burst Order Control Power Down Control Note: There is a pull-down device on the ZZ pin, so this input pin can be unconnected and the chip will operate in the default states as specified in ...

Page 8

Byte Write Truth Table Function GW Read H Read H Write byte a H Write byte b H Write byte c H Write byte d H Write all bytes H Write all bytes L Notes: 1. All byte outputs are ...

Page 9

Synchronous Truth Table Address Operation Used Deselect Cycle, Power Down Deselect Cycle, Power Down Deselect Cycle, Power Down Read Cycle, Begin Burst External Read Cycle, Begin Burst External Write Cycle, Begin Burst External Read Cycle, Continue Burst Read Cycle, Continue ...

Page 10

Notes: 1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low. 2. The upper portion of the diagram assumes active use of only the Enable (E1) and Write (B that ADSP is tied ...

Page 11

Notes: 1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from Read cycles ...

Page 12

Absolute Maximum Ratings (All voltages reference Symbol DDQ V I/O V Voltage on Other Input Pins IN I Input Current on Any Pin IN I Output Current on Any I/O Pin OUT P ...

Page 13

V Range Logic Levels DDQ3 Parameter V Input High Voltage DD V Input Low Voltage DD V I/O Input High Voltage DDQ V I/O Input Low Voltage DDQ Notes: 1. The part numbers of Industrial Temperature Range versions end the ...

Page 14

Undershoot Measurement and Timing 50% V – 2 50% tKC Capacitance 2 Parameter Input Capacitance Input/Output Capacitance Note: ...

Page 15

DC Electrical Characteristics Parameter Input Leakage Current (except mode pins) ZZ Input Current FT Input Current Output Leakage Current Output High Voltage Output High Voltage Output Low Voltage Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For ...

Page 16

Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS880F18/32/36AT-5.5/6/6.5/7/7.5/8.5 16/23 © 2001, GSI Technology ...

Page 17

AC Electrical Characteristics Parameter Symbol Clock Cycle Time Clock to Output Valid Clock to Output Invalid Flow Through Clock to Output in Low-Z Setup time Hold time Clock HIGH Time Clock LOW Time Clock to Output in High ...

Page 18

Begin Read A Cont Single Read Single Read CK ADSP tS tH ADSC tS ADV tS tH A0– Ba– tOE DQa–DQd Rev: 1.03 11/2004 Specifications cited ...

Page 19

... During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates normally after ZZ recovery time. ...

Page 20

TQFP Package Drawing (Package T) Symbol Description Min. Nom. Max A1 Standoff 0.05 A2 Body Thickness 1.35 b Lead Width 0.20 c Lead Thickness 0.09 D Terminal Dimension 21.9 D1 Package Body 19.9 E Terminal Dimension 15.9 E1 Package Body ...

Page 21

... GS880F32AT-7.5I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS880F18AT-150IT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow through mode-selectable by the user ...

Page 22

... GS880F36AT-8.5I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS880F18AT-150IT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow through mode-selectable by the user ...

Page 23

... Sync SRAM Datasheet Revision History DS/DateRev. Code: Old; Types of Changes New Format or Content 880F18A_r1 880F18A_r1; 880F18A_r1_01 880F18A_r1_01; 880F18A_r1_02 880F18A_r1_02; 880F18A_r1_03 Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. • Creation of new datasheet • Updated FT power numbers • ...

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