GS864418 GSI [GSI Technology], GS864418 Datasheet
GS864418
Related parts for GS864418
GS864418 Summary of contents
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... ZZ signal stopping the clock (CK). Memory data is retained during Sleep mode. Core and Interface Voltages The GS864418/36/72 operates 3.3 V power supply. All input are 3.3 V and 2.5 V compatible. Separate output power (V pins are used to decouple output noise from the internal circuits and are 3 ...
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... TMS D D Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS864418(B/E)/GS864436(B/E)/GS864472( ADSP ADSC ADV ...
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... SCD I I MCH Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS864418(B/E)/GS864436(B/E)/GS864472(C) Description Address field LSBs and Address Counter Preset Inputs. Address Inputs Data Input and Output pins Byte Write Enable for I/Os ...
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... V I DDQ Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS864418(B/E)/GS864436(B/E)/GS864472(C) Description Must Connect Low Byte Enable; active low FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [Low Drive]) ...
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... SCD V DDQ LBO Bump BGA— Body—1.0 mm Bump Pitch Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS864418(B/E)/GS864436(B/E)/GS864472( ADSC ...
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... SCD V DDQ LBO Bump BGA— Body—1.0 mm Bump Pitch Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS864418(B/E)/GS864436(B/E)/GS864472( ADSC ...
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... GS864418/36 165-Bump BGA Pin Description Symbol Type I — ADV I ADSC, ADSP LBO I FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [Low ...
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... V M DDQ DDQ Bump BGA— Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS864418(B/E)/GS864436(B/E)/GS864472( ADSP ADSC ...
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... GS864418B Pad Out—119-Bump BGA—Top View (Package DDQ DDQ DDQ DDQ DDQ Bump BGA— Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. ...
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... GS864418/36 119-Bump BGA Pin Description Symbol Type I — ADV I ADSP, ADSC LBO I FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [Low ...
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... Power Down ZZ Control Note: Only x36 version shown for simplicity. Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS864418(B/E)/GS864436(B/E)/GS864472(C) GS864418/36/72 Block Diagram Counter Load Register D Q Register ...
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... Note: The burst counter wraps to initial state on the 5th clock. Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS864418(B/E)/GS864436(B/E)/GS864472(C) Pin Name State L LBO ...
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... All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs. 4. Bytes “ ” and “ ” are only available on the x36 version Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS864418(B/E)/GS864436(B/E)/GS864472( ...
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... Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above. 6. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above. Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS864418(B/E)/GS864436(B/E)/GS864472(C) State Diagram E 1 ...
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... The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs and assumes ADSP is tied high and ADV is tied low. Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS864418(B/E)/GS864436(B/E)/GS864472(C) Simplified State Diagram X Deselect ...
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... Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet Data Input Set Up Time. Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS864418(B/E)/GS864436(B/E)/GS864472(C) Simplified State Diagram with G X Deselect ...
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... Input Under/overshoot voltage must be –2 V > Vi < V Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS864418(B/E)/GS864436(B/E)/GS864472(C) Description Voltage on V Pins DD ...
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... Input Under/overshoot voltage must be –2 V > Vi < V Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS864418(B/E)/GS864436(B/E)/GS864472(C) Symbol Min. Typ. V 2.0 — ...
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... Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted. 3. Device is deselected as defined by the Truth Table. Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS864418(B/E)/GS864436(B/E)/GS864472(C) Overshoot Measurement and Timing 50% ...
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... ZZ Input Current FT, SCD, and ZQ Input Current Output Leakage Current Output High Voltage Output High Voltage Output Low Voltage Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS864418(B/E)/GS864436(B/E)/GS864472(C) Symbol Test Conditions ≥ ...
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... Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS864418(B/E)/GS864436(B/E)/GS864472(C) 21/41 Product Preview © 2003, GSI Technology ...
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... asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold times as specified above. Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS864418(B/E)/GS864436(B/E)/GS864472(C) -250 -225 Min ...
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... tOE DQa–DQd Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS864418(B/E)/GS864436(B/E)/GS864472(C) Pipeline Mode Timing (SCD) Cont Deselect Write B Read C Single Write Single Write tKL tKL tKH tKH tKC ...
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... tOE DQa–DQd Q(A) Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS864418(B/E)/GS864436(B/E)/GS864472(C) Flow Through Mode Timing (SCD) Cont Write B Read C Read C+1 Read C+2 Read C+3 Read C tKL tKL tKC tKC Fixed High ...
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... tOE DQa–DQd Hi-Z Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS864418(B/E)/GS864436(B/E)/GS864472(C) Pipeline Mode Timing (DCD) Deselect Deselect Write B Read C Read C+1 Read C+2 Read C+3 Cont tKL tKL tKH tKH tKC tKC ...
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... SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates normally after ZZ recovery time. Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS864418(B/E)/GS864436(B/E)/GS864472(C) Flow Through Mode Timing (DCD) Deselect Write B Read C ...
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... TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG Port unused, TCK, TDI, and TMS may be left floating or tied to either V Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS864418(B/E)/GS864436(B/E)/GS864472(C) Sleep Mode Timing Diagram tKH tKH ...
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... Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z, SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register. Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS864418(B/E)/GS864436(B/E)/GS864472(C) Description 28/41 Product Preview ...
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... x16 Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS864418(B/E)/GS864436(B/E)/GS864472(C) JTAG TAP Block Diagram (2-die module) · · · · · · TDO TDI Not Used ...
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... TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facili- tate testing of other devices in the scan path. Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS864418(B/E)/GS864436(B/E)/GS864472(C) JTAG Tap Controller State Diagram 1 1 ...
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... Z) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state. RFU These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction. Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS864418(B/E)/GS864436(B/E)/GS864472(C) 31/41 Product Preview © 2003, GSI Technology ...
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... Places Bypass Register between TDI and TDO. Notes: 1. Instruction codes expressed in binary, MSB on left, LSB on right. 2. Default instruction automatically loaded at power-up and in test-logic-reset state. Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS864418(B/E)/GS864436(B/E)/GS864472(C) Conditions V – V/ns ...
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... OLJ –100 uA OHJC +100 uA OHJC TCK TDI TMS TDO Parallel SRAM input Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS864418(B/E)/GS864436(B/E)/GS864472(C) Symbol V IHJ3 V ILJ3 V IHJ2 V ILJ2 I INHJ I INLJ I OLJ V ...
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... For information regarding the Boundary Scan Chain obtain BSDL files for this part, please contact our Applications Engineering Department at: apps@gsitechnology.com. Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS864418(B/E)/GS864436(B/E)/GS864472(C) Min Max Unit 50 — ...
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... Symbol Min Typ A — — A1 0.40 0.50 ∅b 0.50 0.60 c 0.31 0.36 D 21.9 22.0 Rev 1.0 Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS864418(B/E)/GS864436(B/E)/GS864472(C) 209 BGA Package Drawing (Package ∅b e Max Units Symbol 22.1 mm ...
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... SEATING PLANE C Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS864418(B/E)/GS864436(B/E)/GS864472(C) BOTTOM VIEW A1 Ø0. Ø0. Ø0.60~0.90 (119x 7.62 14±0. ...
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... SEATING PLANE C Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS864418(B/E)/GS864436(B/E)/GS864472(C) BOTTOM VIEW Ø0. Ø0. Ø0.44~0.64(165x 1.0 10.0 15±0. ...
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... GS864436E-133 Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS864418B-150IB. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user ...
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... GS864436E-225I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS864418B-150IB. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user ...
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... GS864472C-133I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS864418B-150IB. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user ...
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... Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS864418(B/E)/GS864436(B/E)/GS864472(C) Types of Changes Format or Content • Creation of new datasheet • Updated Operating Currents table Content • Updated FT AC Characteristics for tKQ • ...