GS880F18T GSI [GSI Technology], GS880F18T Datasheet

GS880F18T

Manufacturer Part Number

GS880F18T

Description

512K x 18, 256K x 36 8Mb Sync Burst SRAMs

Manufacturer

GSI [GSI Technology]

Datasheet

1.GS880F18T.pdf (25 pages)

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100 Pin TQFP

Commercial Temp

Industrial Temp

Features

• Flow through mode operation.

• 3.3V +10%/-5% Core power supply.

• 2.5V or 3.3V I/O supply.

• LBO pin for linear or interleaved burst mode.

• Internal input resistors on mode pins allow floating mode pins.

• Byte write (BW) and/or global write (GW) operation.

• Common data inputs and data outputs.

• Clock Control, registered, address, data, and control.

• Internal Self-Timed Write cycle.

• Automatic power-down for portable applications.

• 100-lead TQFP package

Functional Description

Applications

The GS880F18/32/36T is a 9,437,184 bit (8,388,608 bit for x32

version) high performance synchronous SRAM with a 2 bit burst

address counter. Although of a type originally developed for Level 2

Cache applications supporting high performance CPU’s, the device

now finds application in synchronous SRAM applications ranging from

DSP main store to networking chip set support.

Controls

Addresses, data I/O’s, chip enables (E1, E2, E3), address burst

control inputs (ADSP, ADSC, ADV) and write control inputs (Bx, BW,

GW) are synchronous and are controlled by a positive edge triggered

clock input (CK). Output enable (G) and power down control (ZZ) are

asynchronous inputs. Burst cycles can be initiated with either ADSP

or ADSC inputs. In Burst mode, subsequent burst addresses are

generated internally and are controlled by ADV. The burst address

counter may be configured to count in either linear or interleave order

with the Linear Burst Order (LBO) input. The Burst function need not

be used. New addresses can be loaded on every cycle with no

degradation of chip performance.

Designing For Compatibility

The JEDEC Standard for Burst RAMS calls for a FT mode pin option

(pin 14 on TQFP). Board sites for Flow through Burst RAMS should

be designed with V

Rev: 1.03 3/2000

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Flow Through

Default to Interleaved Pipelined Mode.

2-1-1-1

tCycle

connected to the FT pin location to ensure the

225mA

10ns

-10

180mA

15ns

11ns

-11

180mA

11.5ns

-11.5

15ns

8Mb Sync Burst SRAMs

512K x 18, 256K x 36

180mA

12ns

15ns

-12

175mA

14ns

15ns

-14

1/25

broadest access to multiple vendor sources. Boards designed with FT

pin pads tied low may be stuffed with GSI’s Pipeline/Flow through

configurable Burst RAMS or any vendor’s Flow through or

configurable Burst SRAM. Bumps designed with the FT pin location

tied High or floating must employ a non-configurable Flow through

Burst RAM, like this RAM, to achieve Flow through functionality.

88018/32/36T

Byte write operation is performed by using byte write enable (BW)

input combined with one or more individual byte write signals (Bx). In

addition, Global Write (GW) is available for writing all bytes at one

time, regardless of the Byte Write control inputs.

Sleep Mode

Low power (Sleep mode) is attained through the assertion (High) of

the ZZ signal, or by stopping the clock (CK). Memory data is retained

during Sleep mode.

Core and Interface Voltages

The GS880F18/32/36T operates on a 3.3V power supply and all

inputs/outputs are 3.3V and 2.5V compatible. Separate output power

circuit.

DDQ

) pins are used to de-couple output noise from the internal

Byte Write and Global Write

GS880F18/36T-10/11/11.5/12/14

3.3V & 2.5V I/O

Preliminary

10ns - 14ns

3.3V VDD

Related parts for GS880F18T

GS880F18T Summary of contents

Page 1

... Functional Description Applications The GS880F18/32/36T is a 9,437,184 bit (8,388,608 bit for x32 version) high performance synchronous SRAM with a 2 bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPU’s, the device now finds application in synchronous SRAM applications ranging from DSP main store to networking chip set support ...

Page 2

GS880F18 100 Pin TQFP Pinout 100 DDQ ...

Page 3

GS880F32 100 Pin TQFP Pinout 100 DDQ ...

Page 4

GS880F36 100 Pin TQFP Pinout 100 DDQ ...

Page 5

TQFP Pin Description Pin Location 37, 36 35, 34, 33, 32, 100, 99, 82, 81, 44, 45, 46, 47, 48, 49, 50 63, 62, 59, 58, 57, 56, 53, 52 68, 69, 72, 73, 74, 75, 78, 79 ...

Page 6

GS880F18/32/36 Block Diagram Register A0- LBO ADV CK ADSC ADSP Power Down ZZ Control Note: Only x36 version ...

Page 7

Mode Pin Functions Mode Name Pin Name State Burst Order Control Power Down Control Note: There is a pull up device on the LBO pin and a pull down device on the ZZ pin, so those input pins can be ...

Page 8

Synchronous Truth Table Address Operation Used Deselect Cycle, Power None Down Deselect Cycle, Power Down None Deselect Cycle, Power None Down Read Cycle, Begin Burst External Read Cycle, Begin Burst External Write Cycle, Begin Burst External Read Cycle, Continue Burst ...

Page 9

Simplified State Diagram Notes: 1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied Low. 2. The upper portion of the diagram assumes active use of only the Enable (E1E2) and Write (B and ...

Page 10

Simplified State Diagram with G Notes: 1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use Use of “Dummy Reads” (Read Cycles with G High) may be used to make ...

Page 11

Absolute Maximum Ratings ) (All voltages reference Symbol Description V Voltage Voltage in V DDQ DDQ V Voltage on Clock Input Pin CK V Voltage on I/O Pins I/O V Voltage on Other ...

Page 12

... Junction to Ambient (at 200 lfm) Junction to Ambient (at 200 lfm) Junction to Case (TOP) Notes: 1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient. Temper- ature air flow, board density, and PCB thermal resistance. 2. SCMI G-38-87. 3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1. ...

Page 13

Output Load Electrical Characteristics Symb Parameter ol Input Leakage Current I IL (except mode pins Input Current INZZ I Mode Pin Input Current INM I Output Leakage Current Output High Voltage OH ...

Page 14

Absolute Maximum Ratings ) (All voltages reference Symbol Description V Voltage Voltage in V DDQ DDQ V Voltage on Clock Input Pin CK V Voltage on I/O Pins I/O V Voltage on Other ...

Page 15

Page 16

Page 17

AC Electrical Characteristics Parameter Clock Cycle Time Clock to Output Valid Flow- Thru Clock to Output Invalid Clock to Output in Low-Z Clock HIGH Time Clock LOW Time Clock to Output in High Output Valid G to output ...

Page 18

Write Cycle Timing Single Write ADSP tS tH ADSC tS tH ADV ADV must be inactive for ADSP Write WR1 ...

Page 19

Flow Through Read-Write Cycle Timing Single Read ADSP ADSC ADV RD1 tOE ...

Page 20

Flow Through Read Cycle Timing Single Read ADSP ADSC ADV RD1 ...

Page 21

Sleep Mode Timing Diagram ADSP ADSC ZZ Rev: 1.03 3/2000 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. tKC tKH tKL tZZH tZZS Snooze 21/25 Preliminary GS880F18/36T-10/11/11.5/12/14 tZZR © 2000, Giga Semiconductor, ...

Page 22

Output Driver Characteristics 120.0 100.0 Pull Down Drivers 80.0 60.0 40.0 20.0 0.0 -20.0 -40.0 -60.0 Pull Up Drivers -80.0 -100.0 -120.0 -140.0 -0 Rev: 1.03 3/2000 Specifications cited are subject to change without notice. For ...

Page 23

TQFP Package Drawing Symbol Description Min. A1 Standoff 0.05 A2 Body Thickness 1.35 b Lead Width 0.20 c Lead Thickness 0.09 D Terminal Dimension 21.9 D1 Package Body 19.9 E Terminal Dimension 15.9 E1 Package Body 13.9 e Lead Pitch ...

Page 24

... GS880F36T-10 256K x 36 GS880F36T-11 256K x 36 GS880F36T--11.5 256K x 36 GS880F36T-12 256K x 36 GS880F36T-14 512K x 18 GS880F18T-10I 512K x 18 GS880F18T-11I 512K x 18 GS880F18T--11.5I 512K x 18 GS880F18T-12I 512K x 18 GS880F18T-14I 256K x 32 GS880F32T-10 256K x 32 GS880F32T-11 256K x 32 GS880F32T--11.5 256K x 32 ...

Page 25

Revision History Types of Changes DS/DateRev. Code: Old; Format or Content New GS880F18/36 1.00 11/1999J GS880F18/36T 1.00 880F18/36T K 1.02 1/2000L GS880F1836T Rev. 1.02 1/2000L; GS880F1836T Rev. 1.03 3/2000N Rev: 1.03 3/2000 Specifications cited are subject to change without notice. ...

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