GS8320Z18GT-133I GSI [GSI Technology], GS8320Z18GT-133I Datasheet
GS8320Z18GT-133I
Related parts for GS8320Z18GT-133I
GS8320Z18GT-133I Summary of contents
Page 1
... For read cycles, pipelined SRAM output data is temporarily stored by the edge triggered output register during the access cycle and then released to the output drivers at the next rising edge of clock ...
Page 2
DDQ ...
Page 3
DQP DDQ ...
Page 4
TQFP Pin Descriptions Symbol Type ...
Page 5
... GS8320Z18/36 NBT SRAM Functional Block Diagram Rev: 1.03 10/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8320Z18/36T-250/225/200/166/150/133 Amps Sense Drivers Write 5/24 Preliminary © 2001, GSI Technology ...
Page 6
... A B cycle with no Byte Write inputs active is a no-op cycle. The pipelined NBT SRAM provides double late write functionality, matching the write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At the first rising edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is required at the third rising edge of clock ...
Page 7
... Dummy Read and Write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs when the W pin is sampled low but no Byte Write pins are active so no write operation is performed can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during write cycles. 4. ...
Page 8
Pipeline and Flow Through Read Write Control State Diagram New Read R R Burst Read B Key Input Command Code ƒ Transition Current State (n) Next State (n+1) n Clock (CK) Command Current State Current State and Next State Definition ...
Page 9
Intermediate B W High Z (Data In) Key Input Command Code ƒ Transition Current State (n) Intermediate State (N+1) Clock (CK) Command Current State and Next State Definition for Rev: 1.03 10/2004 Specifications cited are subject to change without notice. ...
Page 10
B W High Z (Data In) Key Input Command Code ƒ Transition Current State (n) Clock (CK) Command Current State and Next State Definition for: Rev: 1.03 10/2004 Specifications cited are subject to change without notice. For latest documentation see ...
Page 11
... SRAM to advance the internal address counter and use the counter generated address to read or write the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into Load mode ...
Page 12
... During normal operation, ZZ must be pulled low, either by the user or by it’s internal pull down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates normally after 2 cycles of wake up time. ...
Page 13
Absolute Maximum Ratings (All voltages reference Symbol DDQ V I/O V Voltage on Other Input Pins IN I Input Current on Any Pin IN I Output Current on Any I/O Pin OUT P ...
Page 14
V Range Logic Levels DDQ3 Parameter V Input High Voltage DD V Input Low Voltage DD V I/O Input High Voltage DDQ V I/O Input Low Voltage DDQ Notes: 1. The part numbers of Industrial Temperature Range versions end the ...
Page 15
Undershoot Measurement and Timing 50% V – 2 20% tKC Capacitance 2 Parameter Input Capacitance Input/Output Capacitance Note: ...
Page 16
DC Electrical Characteristics Parameter Input Leakage Current (except mode pins) ZZInput Current Output Leakage Current (x36/x72) Output Leakage Current (x18) Output High Voltage Output High Voltage Output Low Voltage Rev: 1.03 10/2004 Specifications cited are subject to change without notice. ...
Page 17
Rev: 1.03 10/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8320Z18//36T-250/225/200/166/150/133 17/24 Preliminary © 2001, GSI Technology ...
Page 18
AC Electrical Characteristics Parameter Symbol Clock Cycle Time Clock to Output Valid Clock to Output Invalid Pipeline Clock to Output in Low-Z Setup time Hold time Clock Cycle Time Clock to Output Valid Clock to Output Invalid Flow Through Clock ...
Page 19
Write A Write CKE ADV A0– DQa–DQd G *Note: E=High(False ...
Page 20
Write A Write CKE ADV A0– D(A) G *Note High(False ...
Page 21
TQFP Package Drawing (Package T) Symbol Description Min. Nom. Max A1 Standoff 0.05 A2 Body Thickness 1.35 b Lead Width 0.20 c Lead Thickness 0.09 D Terminal Dimension 21.9 D1 Package Body 19.9 E Terminal Dimension 15.9 E1 Package Body ...
Page 22
... GS8320Z18GT-225 GS8320Z18GT-200 GS8320Z18GT-166 GS8320Z18GT-150 GS8320Z18GT-133 Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8320Z36T-166IT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user ...
Page 23
... GS8320Z36GT-150 GS8320Z36GT-133 GS8320Z18GT-250I GS8320Z18GT-225I GS8320Z18GT-200I GS8320Z18GT-166I GS8320Z18GT-150I GS8320Z18GT-133I GS8320Z36GT-250I GS8320Z36GT-225I GS8320Z36GT-200I GS8320Z36GT-166I GS8320Z36GT-150I GS8320Z36GT-133I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8320Z36T-166IT. ...
Page 24
... Sync SRAM Datasheet Revision History DS/DateRev. Code: Old; Types of Changes New Format or Content 8320Z18_r1 8320Z18_r1; 8320Z18_r1_01 8320Z18_r1_01; 8320Z18_r1_02 8320Z18_r1_02; 8320Z18_r1_03 Rev: 1.03 10/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8320Z18/36T-250/225/200/166/150/133 Page;Revisions;Reason • Creation of new datasheet • ...