GS820H32Q-4I GSI [GSI Technology], GS820H32Q-4I Datasheet - Page 16

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GS820H32Q-4I

Manufacturer Part Number
GS820H32Q-4I
Description
64K x 32 2M Synchronous Burst SRAM
Manufacturer
GSI [GSI Technology]
Datasheet
Rev: 1.03 2/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Flow Through Read-Write Cycle Timing
DQ
A
B
ADSC
A0-An
ADSP
- DQ
A
ADV
- B
GW
BW
CK
E
E
E
G
D
D
1
2
3
Hi-Z
tS tH
tS
tS tH
tS
tS
RD1
tH
tH
tH
tKQ
Single Read
tOE
tS tH
tS tH
tS
Q1
tOHZ
A
E2 and E3 only sampled with ADSP and ADSC
tKH
16/23
tKL
tH
tKC
Single Write
tS
tS tH
tS tH
WR1
WR1
D1
A
tH
RD2
ADSC initiated read
GS820H32T/Q-150/138/133/117/100/66
ADSP is blocked by E inactive
Burst wrap around to it’s initial state
Q2
A
E1 masks ADSP
Burst Read
Q2
B
© 1999, Giga Semiconductor, Inc.
Deselected with E3
Q2
C
Q2
D
Q2
A
D

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