GS8320Z18GT-200V GSI [GSI Technology], GS8320Z18GT-200V Datasheet
GS8320Z18GT-200V
Related parts for GS8320Z18GT-200V
GS8320Z18GT-200V Summary of contents
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... The GS8320Z18/36T-xxxV is a 36Mbit Synchronous Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other pipelined read/double late write or flow through read/ single late write SRAMs, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles. ...
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DDQ ...
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DQP DDQ ...
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TQFP Pin Descriptions Symbol Type ...
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... GS8320Z18/36T-xxxV NBT SRAM Functional Block Diagram Rev: 1.02 5/2006 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Amps Sense Drivers Write 5/23 Preliminary GS8320Z18/36T-xxxV © 2001, GSI Technology ...
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... A B cycle with no Byte Write inputs active is a no-op cycle. The pipelined NBT SRAM provides double late write functionality, matching the write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At the first rising edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is required at the third rising edge of clock ...
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... Dummy Read and Write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs when the W pin is sampled low but no Byte Write pins are active so no write operation is performed can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during write cycles. 4. ...
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Pipeline and Flow Through Read Write Control State Diagram New Read R R Burst Read B Key Input Command Code ƒ Transition Current State (n) Next State (n+1) n Clock (CK) Command Current State Current State and Next State Definition ...
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Intermediate B W High Z (Data In) Key Input Command Code ƒ Transition Current State (n) Intermediate State (N+1) Clock (CK) Command Current State and Next State Definition for Rev: 1.02 5/2006 Specifications cited are subject to change without notice. ...
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B W High Z (Data In) Key Input Command Code ƒ Transition Current State (n) Clock (CK) Command Current State and Next State Definition for: Rev: 1.02 5/2006 Specifications cited are subject to change without notice. For latest documentation see ...
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... SRAM to advance the internal address counter and use the counter generated address to read or write the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into Load mode ...
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... During normal operation, ZZ must be pulled low, either by the user or by it’s internal pull down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates normally after 2 cycles of wake up time. ...
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Absolute Maximum Ratings (All voltages reference Symbol Voltage on V DDQ V I/O V Voltage on Other Input Pins IN I Input Current on Any Pin IN I Output Current on Any I/O ...
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V & V Range Logic Levels DDQ2 DDQ1 Parameter V Input High Voltage DD V Input Low Voltage DD Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica- tions ...
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AC Test Conditions Parameter Input high level Input low level Input slew rate Input reference level Output reference level Output load Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. ...
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Rev: 1.02 5/2006 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. 16/23 Preliminary GS8320Z18/36T-xxxV © 2001, GSI Technology ...
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AC Electrical Characteristics Parameter Symbol Clock Cycle Time Clock to Output Valid Clock to Output Invalid Pipeline Clock to Output in Low-Z Setup time Hold time Clock Cycle Time Clock to Output Valid Clock to Output Invalid Flow Through Clock ...
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Write A Read CKE ADV Rev: 1.02 5/2006 Specifications cited are subject to change without notice. For latest documentation ...
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Write A Write CKE ADV A0– D(A) G *Note High(False ...
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TQFP Package Drawing (Package T) Symbol Description Min. Nom. Max A1 Standoff 0.05 A2 Body Thickness 1.35 b Lead Width 0.20 c Lead Thickness 0.09 D Terminal Dimension 21.9 D1 Package Body 19.9 E Terminal Dimension 15.9 E1 Package Body ...
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... GS8320Z36T-150IV GS8320Z36T-133IV GS8320Z18GT-250V GS8320Z18GT-225V GS8320Z18GT-200V GS8320Z18GT-166V GS8320Z18GT-150V Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8320Z36T-166IT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user ...
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... GS8320Z36GT-200V GS8320Z36GT-166V GS8320Z36GT-150V GS8320Z36GT-133V GS8320Z18GT-250IV GS8320Z18GT-225IV GS8320Z18GT-200IV GS8320Z18GT-166IV GS8320Z18GT-150IV GS8320Z18GT-133IV GS8320Z36GT-250IV GS8320Z36GT-225IV GS8320Z36GT-200IV GS8320Z36GT-166IV GS8320Z36GT-150IV GS8320Z36GT-133IV Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8320Z36T-166IT. ...
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... Sync SRAM Datasheet Revision History DS/DateRev. Code: Old; Types of Changes New Format or Content 8320ZV18_r1 8320ZV18_r1; 8320ZV18_r1_01 8320ZV18_r1_01; 8320Zxx_V_r1_02 Rev: 1.02 5/2006 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Page;Revisions;Reason • Creation of new datasheet • Updated format Content/Format • ...