GS832118E GSI [GSI Technology], GS832118E Datasheet
GS832118E
Related parts for GS832118E
GS832118E Summary of contents
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... Pb-Free 165-bump BGA package available Functional Description Applications The GS832118/32/36E is a 37,748,736-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support ...
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Bump BGA—x18 Commom I/O—Top View (Package DDQ D NC DQB V DDQ E NC DQB V DDQ F NC DQB V DDQ G ...
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Bump BGA—x32 Common I/O—Top View (Package DDQ D DQC DQC V DDQ E DQC DQC V DDQ F DQC DQC V DDQ G ...
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Bump BGA—x36 Common I/O—Top View (Package DQPC NC V DDQ D DQC DQC V DDQ E DQC DQC V DDQ F DQC DQC V DDQ G ...
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GS832118/32/36E 165-Bump BGA Pin Description Symbol Type I — ...
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Register – LBO ADV CK ADSC ADSP Power Down ZZ Control Note: Only x36 version shown for simplicity. Rev: 1.03 ...
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Mode Pin Functions Mode Name Burst Order Control Output Register Control Power Down Control Note: There are pull-up devices on the FT pin and a pull-down device on the ZZ pin, so those input pins can be unconnected and the ...
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Byte Write Truth Table Function GW Read H Read H Write byte a H Write byte b H Write byte c H Write byte d H Write all bytes H Write all bytes L Notes: 1. All byte outputs are ...
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Synchronous Truth Table Operation Address Used Deselect Cycle, Power Down Read Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst Read Cycle, ...
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Notes: 1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low. 2. The upper portion of the diagram assumes active use of only the Enable (E1) and Write (B that ADSP is tied ...
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Notes: 1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from read cycles ...
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Absolute Maximum Ratings (All voltages reference Symbol Voltage in V DDQ V I/O V Voltage on Other Input Pins IN I Input Current on Any Pin IN I Output Current on Any I/O ...
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V Range Logic Levels DDQ3 Parameter V Input High Voltage DD V Input Low Voltage DD V I/O Input High Voltage DDQ V I/O Input Low Voltage DDQ Notes: 1. The part numbers of Industrial Temperature Range versions end the ...
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Undershoot Measurement and Timing 50% V – 2 20% tKC Capacitance 2 Parameter Input Capacitance Input/Output Capacitance Note: ...
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DC Electrical Characteristics Parameter Input Leakage Current (except mode pins) ZZ Input Current FT, SCD, ZQInput Current Output Leakage Current (x36/x72) Output Leakage Current (x18) Output High Voltage Output High Voltage Output Low Voltage Rev: 1.03 4/2005 Specifications cited are ...
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Rev: 1.03 4/2005 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS832118/32/36E-250/225/200/166/150/133 16/32 © 2003, GSI Technology ...
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AC Electrical Characteristics Parameter Symbol Clock Cycle Time Clock to Output Valid Clock to Output Invalid Pipeline Clock to Output in Low-Z Setup time Hold time Clock Cycle Time Clock to Output Valid Clock to Output Invalid Flow Through Clock ...
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Begin Read A Cont Single Read Single Read CK ADSP tS tH ADSC tS ADV tS tH A0– Ba– tOE DQa–DQd Rev: 1.03 4/2005 Specifications cited ...
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Begin Read A Cont tKH tKH CK ADSP tS tH ADSC tS tH ADV tS tH A0– Ba– and E3 only sampled with ADSC tOE ...
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... During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates normally after ZZ recovery time. ...
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JTAG Pin Descriptions Pin Pin Name I/O Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate TCK Test Clock In from the falling edge of TCK. The TMS input is sampled ...
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TDI TMS TCK Identification (ID) Register The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in Capture-DR state with the IDCODE command loaded ...
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Tap Controller Instruction Set Overview There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific (Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be implemented in ...
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SAMPLE/PRELOAD SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and I/O buffers into ...
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JTAG TAP Instruction Set Summary Instruction Code EXTEST 000 Places the Boundary Scan Register between TDI and TDO. IDCODE 001 Preloads ID Register and places it between TDI and TDO. Captures I/O ring contents. Places the Boundary Scan Register between ...
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JTAG Port Recommended Operating Conditions and DC Characteristics Parameter 3.3 V Test Port Input High Voltage 3.3 V Test Port Input Low Voltage 2.5 V Test Port Input High Voltage 2.5 V Test Port Input Low Voltage TMS, TCK and ...
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... TCK TDI TMS TDO Parallel SRAM input JTAG Port AC Electrical Characteristics Parameter Symbol TCK Cycle Time tTKC TCK Low to TDO Valid tTKQ TCK High Pulse Width tTKH TCK Low Pulse Width tTKL TDI & TMS Set Up Time tTS TDI & TMS Hold Time ...
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Package Dimensions—165-Bump FPBGA (Package E; Variation 1) A1 TOP VIEW SEATING PLANE C ...
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... GS832118E-150I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS832118E-166IT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user ...
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... GS832132GE-133 Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS832118E-166IT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user ...
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... GS832136GE-133I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS832118E-166IT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user ...
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... Sync SRAM Datasheet Revision History DS/DateRev. Code: Old; Types of Changes New Format or Content 8321xx_r1 8321xx_r1; 8321xx_r1_01 8321xx_r1_01; 8321xx_r1_02 8321xx_r1_02; 8321xx_r1_03 Rev: 1.03 4/2005 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS832118/32/36E-250/225/200/166/150/133 • Creation of new datasheet • ...