GS880V37AT GSI [GSI Technology], GS880V37AT Datasheet

no-image

GS880V37AT

Manufacturer Part Number
GS880V37AT
Description
256K x 36 9Mb Sync Burst SRAMs
Manufacturer
GSI [GSI Technology]
Datasheet
100-Pin TQFP
Commercial Temp
Industrial Temp
Features
• Single Cycle Deselect (SCD) operation
• 1.8 V +10%/–10% core power supply
• 1.8 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 100-lead TQFP package
Functional Description
Applications
The GS880V37AT is a 9,437,184-bit high performance
synchronous SRAM with a 2-bit burst address counter.
Although of a type originally developed for Level 2 Cache
applications supporting high performance CPUs, the device
now finds application in synchronous SRAM applications,
ranging from DSP main store to networking chip set support.
Controls
Addresses, data I/Os, chip enables (E1, E2, E3), address burst
control inputs (ADSP, ADSC, ADV), and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
Rev: 1.03 7/2004
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Pipeline
3-1-1-1
1.8 V
9Mb Sync Burst SRAMs
Curr
tCycle
Parameter Synopsis
t
KQ
(x36)
1/18
256K x 36
-250
320
2.5
4.0
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
SCD Pipelined Reads
The GS880V37AT is a SCD (Single Cycle Deselect) pipelined
synchronous SRAM. DCD (Dual Cycle Deselect) versions are
also available. SCD SRAMs pipeline deselect commands one
stage less than read commands. SCD RAMs begin turning off
their outputs immediately after the deselect command has been
captured in the input registers.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS880V37AT operates on a 1.8 V power supply. All input
are 1.8 V compatible. Separate output power (V
used to decouple output noise from the internal circuits and are
1.8 V compatible.
-225
295
2.7
4.4
-200
265
3.0
5.0
Unit
mA
ns
ns
GS880V37AT-250/225/200
© 2002, GSI Technology
250 MHz–200 MHz
DDQ
1.8 V V
) pins are
1.8 V I/O
DD

Related parts for GS880V37AT

GS880V37AT Summary of contents

Page 1

... ZZ signal stopping the clock (CK). Memory data is retained during Sleep mode. Core and Interface Voltages The GS880V37AT operates on a 1.8 V power supply. All input are 1.8 V compatible. Separate output power (V used to decouple output noise from the internal circuits and are 1.8 V compatible. ...

Page 2

... D 30 DQP Rev: 1.03 7/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS880V37A 100-Pin TQFP Pinout 256K x 36 Top View 2/18 GS880V37AT-250/225/200 DQP ...

Page 3

... Address Strobe (Processor, Cache Controller); active low Sleep Mode control; active high Linear Burst Order mode; active low Core power supply I/O and Core Ground Output driver power supply (must be tied high) DDQ Not Use (must be left floating) 3/18 GS880V37AT-250/225/200 © 2002, GSI Technology ...

Page 4

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS880V37A Block Diagram Counter Load Register D Q Register D Q Register D Q Register D Q Register D Q Register D Q Register 4/18 GS880V37AT-250/225/200 A Memory Array – DQx1 DQx9 © 2002, GSI Technology ...

Page 5

... The burst counter wraps to initial state on the 5th clock may be used in any combination with BW to write single or multiple bytes. D 5/18 GS880V37AT-250/225/200 = I SB A[1:0] A[1:0] A[1:0] A[1: Notes ...

Page 6

... None X H None X L None Next CR X Next CR H Next CW X Next 6/18 GS880V37AT-250/225/200 2 ADSP ADSC ADV ...

Page 7

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Simplified State Diagram X Deselect First Write Burst Write CR CW 7/18 GS880V37AT-250/225/200 First Read Burst Read BW, and GW © 2002, GSI Technology ...

Page 8

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Simplified State Diagram with G X Deselect First Write Burst Write 8/18 GS880V37AT-250/225/200 First Read Burst Read CR © 2002, GSI Technology ...

Page 9

... Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component. Rev: 1.03 7/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Description Voltage on V Pins DD Pins DDQ Voltage on I/O Pins 9/18 GS880V37AT-250/225/200 Value –0.5 to 3.6 –0.5 to 3.6 –0.5 to 3.6 –0 +0.5 (≤ 3.6 V max.) DDQ –0 +0.5 (≤ 3.6 V max.) DD +/–20 +/– ...

Page 10

... V 0.6*V — –0.3 — 0.6*V — IHQ DD V –0.3 — ILQ +2 V, with a pulse width not to exceed 20% tKC. DDn Symbol Min –40 A 10/18 GS880V37AT-250/225/200 Typ. Max. Unit 1.8 2.0 V 1.8 2.0 V Max. Unit Notes 0.3 0 DDQ 0.3 Typ ...

Page 11

... V V Symbol Test conditions I/O OUT Conditions V – DDQ Fig. 1 Output Load 1 DQ 50Ω V DDQ/2 * Distributed Test Jig Capacitance 11/18 GS880V37AT-250/225/200 20% tKC DD IL Typ. Max. Unit 30pF © 2002, GSI Technology ...

Page 12

... Mode Symbol to to 70°C 85°C I 290 300 DD Pipeline DDQ I Pipeline Pipeline 12/18 GS880V37AT-250/225/200 Min – ≥ V – ≤ V –1 uA 100 uA IH ≥ V –100 uA IL ≤ V – – 1 – 0.4 V DDQ = 1.6 V — -225 ...

Page 13

... GS880V37AT-250/225/200 -200 Unit Max Min Max 5.0 ns — — 2.7 — 3.0 ns 1.0 ns — — — 1.0 — ns 1.4 ns — — — 0.4 — ns 2.0 2.5 ns — 2.0 — ...

Page 14

... Pipeline Mode Timing (+1) Cont Deselect Write B Read C Read C+1 Read C+2 Read C+3 Cont tKC tKC tKH tKH tKL tKL ADSC initiated read and E3 only sampled with ADSC tS tKQ tOHZ tH Q(A) D(B) 14/18 GS880V37AT-250/225/200 Deselect Deselected with E1 tKQX tLZ tHZ Q(C) Q(C+1) Q(C+2) Q(C+3) © 2002, GSI Technology ...

Page 15

... Rev: 1.03 7/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Sleep Mode Timing Diagram tKH tKH tKC tKC tKL tKL tZZS tZZH 15/18 GS880V37AT-250/225/200 2. The duration of SB tZZR © 2002, GSI Technology ...

Page 16

... Rev: 1.03 7/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. θ 0.10 0.15 1.40 1.45 0.30 0.40 — 0.20 e 22.0 22.1 20.0 20.1 16.0 16.1 b 14.0 14.1 0.65 — 0.60 0.75 1.00 — 0.10 — 7° Thermal Characteristics Junction to Ambient (θJa) ( C/W) ° 0 m/s 1 m/s 20.4 19.1 16/18 GS880V37AT-250/225/200 E1 E Junction to Case (θJc) ( C/W) ° 2 m/s 17.2 3.6 © 2002, GSI Technology ...

Page 17

... GS880V37AT-225I 256K x 36 GS880V37AT-200I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS880V37AT-200IT Commercial Temperature Range GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet ...

Page 18

... Updated tKQ in table on page 1 and in AC Characteristics Content table on page 13 • Updated timing diagram • Corrected ordering information (added “V” to part number) Content • Updated format Content/Format • Removed Preliminary banner due to part qualification 18/18 GS880V37AT-250/225/200 Page;Revisions;Reason © 2002, GSI Technology ...

Related keywords