GS880V37BGT-360 GSI [GSI Technology], GS880V37BGT-360 Datasheet

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GS880V37BGT-360

Manufacturer Part Number
GS880V37BGT-360
Description
256K x 36 9Mb Sync Burst SRAMs
Manufacturer
GSI [GSI Technology]
Datasheet
100-Pin TQFP
Commercial Temp
Industrial Temp
Features
• Single Cycle Deselect (SCD) operation
• 1.8 V +10%/–10% core power supply
• 1.8 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 100-lead TQFP package
• Pb-Free 100-lead TQFP package available
Functional Description
Applications
The GS880V37BT is a 9,437,184-bit high performance
synchronous SRAM with a 2-bit burst address counter.
Although of a type originally developed for Level 2 Cache
applications supporting high performance CPUs, the device
now finds application in synchronous SRAM applications,
ranging from DSP main store to networking chip set support.
Controls
Addresses, data I/Os, chip enables (E1, E2, E3), address burst
control inputs (ADSP, ADSC, ADV), and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Rev: 1.02 10/2004
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Pipeline
3-1-1-1
1.8 V
9Mb Sync Burst SRAMs
Curr
tCycle
Parameter Synopsis
t
KQ
(x36)
1/18
256K x 36
-360
475
1.8
2.8
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
SCD Pipelined Reads
The GS880V37BT is a SCD (Single Cycle Deselect) pipelined
synchronous SRAM. DCD (Dual Cycle Deselect) versions are
also available. SCD SRAMs pipeline deselect commands one
stage less than read commands. SCD RAMs begin turning off
their outputs immediately after the deselect command has been
captured in the input registers.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS880V37BT operates on a 1.8 V power supply. All input
are 1.8 V compatible. Separate output power (V
used to decouple output noise from the internal circuits and are
1.8 V compatible.
-333
435
2.0
3.0
-300
395
2.2
3.3
Unit
mA
ns
ns
GS880V37BT-360/333/300
© 2002, GSI Technology
360 MHz–300 MHz
DDQ
1.8 V V
) pins are
1.8 V I/O
DD

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GS880V37BGT-360 Summary of contents

Page 1

... Pb-Free 100-lead TQFP package available Functional Description Applications The GS880V37BT is a 9,437,184-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support ...

Page 2

DQP DDQ ...

Page 3

TQFP Pin Description Symbol Type I — ...

Page 4

Register – LBO ADV CK ADSC ADSP Power Down ZZ Control Rev: 1.02 10/2004 Specifications cited ...

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Mode Pin Functions Mode Name Burst Order Control Power Down Control Note: There is a pull-down device on the ZZ pin, so this input pin can be unconnected and the chip will operate in the default states as specified in ...

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Synchronous Truth Table Address Operation Used Deselect Cycle, Power Down Deselect Cycle, Power Down Deselect Cycle, Power Down Read Cycle, Begin Burst External Read Cycle, Begin Burst External Write Cycle, Begin Burst External Read Cycle, Continue Burst Read Cycle, Continue ...

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Notes: 1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low. 2. The upper portion of the diagram assumes active use of only the Enable (E1, E2, and E3) and Write (B control ...

Page 8

Notes: 1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from Read cycles ...

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Absolute Maximum Ratings (All voltages reference Symbol DDQ V Voltage on Clock Input Pin CK V I/O V Voltage on Other Input Pins IN I Input Current on Any Pin IN I Output ...

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Power Supply Voltage Ranges Parameter 1.8 V Supply Voltage 1 I/O Supply Voltage DDQ Note: The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst ...

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Undershoot Measurement and Timing 50% V – 2 20% tKC Capacitance 1 Parameter Input Capacitance Input/Output Capacitance Note: ...

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DC Electrical Characteristics Parameter Input Leakage Current (except mode pins) ZZ Input Current Input Current Output Leakage Current Output High Voltage Output Low Voltage Operating Currents Parameter Test Conditions Device Selected; Operating All other inputs Current ≥V or ≤ V ...

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AC Electrical Characteristics Parameter Clock Cycle Time Clock to Output Valid Clock to Output Invalid Clock to Output in Low-Z Pipeline Setup time Hold time G to Output Valid G to output in High-Z Clock HIGH Time Clock LOW Time ...

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Begin Read A Cont CK ADSP tS tH ADSC tS ADV tS tH A0– Ba– tOE DQa–DQd Rev: 1.02 10/2004 Specifications cited are subject to change ...

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... During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates normally after ZZ recovery time. ...

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TQFP Package Drawing (Package T) Symbol Description Min. Nom. Max A1 Standoff 0.05 A2 Body Thickness 1.35 b Lead Width 0.20 c Lead Thickness 0.09 D Terminal Dimension 21.9 D1 Package Body 19.9 E Terminal Dimension 15.9 E1 Package Body ...

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... GS880V37BT-300I 256K x 36 GS880V37BGT-360 256K x 36 GS880V37BGT-333 256K x 36 GS880V37BGT-300 256K x 36 GS880V37BGT-360I 256K x 36 GS880V37BGT-333I 256K x 36 GS880V37BGT-300I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS880V37BT-300IT. 2. ...

Page 18

... Sync SRAM Datasheet Revision History DS/DateRev. Code: Old; Types of Changes New Format or Content 880V37B_r1 880V37B_r1; 880V37B_r1_01 880V37B_r1_01; 880V37B_r1_02 Rev: 1.02 10/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. • Creation of new datasheet • Added 360 MHz Content/Format • ...

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