GS880Z18-V GSI [GSI Technology], GS880Z18-V Datasheet

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GS880Z18-V

Manufacturer Part Number
GS880Z18-V
Description
9Mb Pipelined and Flow Through Synchronous NBT SRAM
Manufacturer
GSI [GSI Technology]
Datasheet
100-Pin TQFP
Commercial Temp
Industrial Temp
Features
• NBT (No Bus Turn Around) functionality allows zero wait
• 1.8 V or 2.5 V +10%/–10% core power supply
• 1.8 V or 2.5 V I/O supply
• User-configurable Pipeline and Flow Through mode
• LBO pin for Linear or Interleave Burst mode
• Pin compatible with 2M, 4M, and 18M devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ Pin for automatic power-down
• JEDEC-standard 100-lead TQFP package
• RoHS-compliant 100-lead TQFP package available
Functional Description
The GS880Z18/32/36BT-xxxV is a 9Mbit Synchronous Static
SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or
other pipelined read/double late write or flow through read/
single late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
Rev: 1.03 6/2006
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
read-write-read bus utilization; Fully pin-compatible with
both pipelined and flow through NtRAM™, NoBL™ and
ZBT™ SRAMs
Flow Through
Pipeline
3-1-1-1
2-1-1-1
9Mb Pipelined and Flow Through
Synchronous NBT SRAM
Curr (x32/x36)
Curr (x32/x36)
Curr (x18)
Curr (x18)
tCycle
tCycle
Paramter Synopsis
t
t
KQ
KQ
1/24
-250
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS880Z18/32/36BT-xxxV may be configured by the user
to operate in Pipeline or Flow Through mode. Operating as a
pipelined synchronous device, meaning that in addition to the
rising edge triggered registers that capture input signals, the
device incorporates a rising-edge-triggered output register. For
read cycles, pipelined SRAM output data is temporarily stored
by the edge triggered output register during the access cycle
and then released to the output drivers at the next rising edge of
clock.
The GS880Z18/32/36BT-xxxV is implemented with GSI's
high performance CMOS technology and is available in a
JEDEC-standard 100-pin TQFP package.
200
230
160
185
3.0
4.0
5.5
5.5
-200
170
195
140
160
3.0
5.0
6.5
6.5
-150
140
160
128
145
3.8
6.7
7.5
7.5
Unit
mA
mA
mA
mA
ns
ns
ns
ns
GS880Z18/32/36BT-xxxV
© 2001, GSI Technology
250 MHz–150 MHz
1.8 V or 2.5 V V
1.8 V or 2.5 V I/O
DD

Related parts for GS880Z18-V

GS880Z18-V Summary of contents

Page 1

... This feature eliminates complex off- chip write pulse generation required by asynchronous SRAMs and simplifies input signal timing. The GS880Z18/32/36BT-xxxV may be configured by the user to operate in Pipeline or Flow Through mode. Operating as a pipelined synchronous device, meaning that in addition to the rising edge triggered registers that capture input signals, the device incorporates a rising-edge-triggered output register ...

Page 2

... GS880Z18BT-xxxV 100-Pin TQFP Pinout (Package T) 100 DDQ DDQ ...

Page 3

... Rev: 1.03 6/2006 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. 256K x 36 Top View 3/24 GS880Z18/32/36BT-xxxV DDQ V 76 ...

Page 4

... DQP Rev: 1.03 6/2006 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. 256K x 36 Top View 4/24 GS880Z18/32/36BT-xxxV DQP DDQ ...

Page 5

... Byte C Data Input and Output pins Byte D Data Input and Output pins Power down control; active high Pipeline/Flow Through Mode Control; active low Linear Burst Order; active low Core power supply Ground Output driver power supply 5/24 GS880Z18/32/36BT-xxxV ; active low A9 ; active low B9 ; active low C9 ; active low D9 ...

Page 6

... GS880Z18/32/36BT-xxxV NBT SRAM Functional Block Diagram Rev: 1.03 6/2006 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Amps Sense Drivers Write 6/24 GS880Z18/32/36BT-xxxV © 2001, GSI Technology ...

Page 7

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com & determine which bytes will be written. All or none may be activated. A write C, D 7/24 GS880Z18/32/36BT-xxxV , E and E ). Deassertion of any one of the Enable © 2001, GSI Technology ...

Page 8

... X Next L None L None L None L None L None L None Current L 8/24 GS880Z18/32/36BT-xxxV High High ...

Page 9

... The Hold command (CKE Low) is not shown because it prevents any state change and D represent input command codes ,as indicated in the Synchronous Truth Table. n+1 n+2 ƒ ƒ Next State Pipeline and Flow Through Read/Write Control State Diagram 9/24 GS880Z18/32/36BT-xxxV New Write Burst Write B D n+3 ƒ ƒ ...

Page 10

... Transition and D represent input command codes as indicated in the Truth Tables. Next State (n+2) n n+1 n+2 ƒ ƒ Intermediate Current State State Pipeline Mode Data I/O State Diagram 10/24 GS880Z18/32/36BT-xxxV Intermediate R B Data Out W (Q Valid) D n+3 ƒ ƒ Next State © 2001, GSI Technology ...

Page 11

... D Next State (n+1) n n+1 ƒ ƒ Current State Next State Pipeline and Flow Through Read Write Control State Diagram 11/24 GS880Z18/32/36BT-xxxV R B Data Out W (Q Valid) D Notes 1. The Hold command (CKE Low) is not shown because it prevents any state change and D represent input command codes as indicated in the Truth Tables ...

Page 12

... Interleaved Burst Sequence 10 11 1st address 11 00 2nd address 00 01 3rd address 01 10 4th address Note: The burst counter wraps to initial state on the 5th clock. 12/24 GS880Z18/32/36BT-xxxV Function Linear Burst Interleaved Burst Flow Through Pipeline Active Standby A[1:0] A[1:0] A[1:0] A[1: ...

Page 13

... GSI NBT SRAMs are fully compatible with these sockets. Pin 66 Connect (NC) on GSI’s GS880Z18B/36 NBT SRAM, the Parity Error open drain output on GSI’s GS881Z18/36B NBT SRAM, is often marked as a power pin on other vendor’s NBT compatible SRAMs. Specifically marked V on pipelined parts and V on flow through parts. Users of GSI NBT devices who are not actually using the ByteSafe™ ...

Page 14

... Voltage on I/O Pins Symbol Min. V 1.7 DD1 V 2.3 DD2 V 1.7 DDQ1 V 2.3 DDQ2 +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. DDn 14/24 GS880Z18/32/36BT-xxxV Value –0.5 to 4.6 –0 –0 +0.5 (≤ 4.6 V max.) DDQ –0 +0.5 (≤ 4.6 V max.) DD +/–20 +/–20 1.5 –55 to 125 –55 to 125 Typ. Max. ...

Page 15

... V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. DDn Overshoot Measurement and Timing Symbol Test conditions I/O OUT 15/24 GS880Z18/32/36BT-xxxV Typ. Max. Unit V + 0.3 V — DD 0.3*V V — DD Typ. Max. Unit ° ° ...

Page 16

... –4 mA, V OH1 –8 mA, V OH2 OH DDQ OL1 OL2 OL 16/24 GS880Z18/32/36BT-xxxV Figure 1 Output Load 1 * 50Ω 30pF V DDQ/2 * Distributed Test Jig Capacitance Min – ≥ –100 –1 uA OUT DD Min = 1 – 0.4 V ...

Page 17

... I Flow Through Pipeline 85 DD — I Flow Through and V operation. DD1 DD2 DDQ1 DDQ2 17/24 GS880Z18/32/36BT-xxxV -250 -200 -150 – –40 0 –40 85°C to 70°C to 85°C to 70°C to 85°C 220 170 190 140 ...

Page 18

... GS880Z18/32/36BT-xxxV -150 Unit Max Min Max — 6.7 — ns 3.0 3.8 ns — 1.5 ns — — 1.5 ns — — — 1.5 — ns 0.5 ns — — 7.5 ns — — 6.5 7.5 ns — ...

Page 19

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Pipeline Mode Timing (NBT) Suspend Read C Write D writeno-op tKH tKH tKC tKC tKL tKL D(A) Q(B) Q(C) 19/24 GS880Z18/32/36BT-xxxV Read E Deselect E tLZ tHZ tKQ tKQX D(D) Q(E) © 2001, GSI Technology ...

Page 20

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Flow Through Mode Timing (NBT) Write B+1 Read C Cont tKL tKL tKH tKH tKC tKC C D tKQ tLZ D(B) D(B+1) Q(C) tOHZ 20/24 GS880Z18/32/36BT-xxxV Read D Write E Read F Write tKQ tKQX tHZ tLZ Q(D) D(E) Q(F) tOLZ tOE © 2001, GSI Technology tKQX D(G) ...

Page 21

... All dimensions are in millimeters (mm). 2. Package width and length do not include mold protrusion. Rev: 1.03 6/2006 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. θ 0.10 0.15 1.40 1.45 0.30 0.40 — 0.20 e 22.0 22.1 20.0 20.1 16.0 16.1 b 14.0 14.1 0.65 — 0.60 0.75 1.00 — 0.10 — 7° 21/24 GS880Z18/32/36BT-xxxV E1 E © 2001, GSI Technology ...

Page 22

... GS880Z36BGT-200V Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: Gs880Z18BT-150IVT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user ...

Page 23

... GS880Z36BGT-150IV Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: Gs880Z18BT-150IVT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user ...

Page 24

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Page;Revisions;Reason • Creation of new datasheet • Added Pb-free information for TQFP Content/Format • 150 MHz speed bin removed Content • Updated entire document to reflect new part nomenclature Content 24/24 GS880Z18/32/36BT-xxxV © 2001, GSI Technology ...

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