GS880Z18BGT-300I GSI [GSI Technology], GS880Z18BGT-300I Datasheet
GS880Z18BGT-300I
Related parts for GS880Z18BGT-300I
GS880Z18BGT-300I Summary of contents
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... For read cycles, pipelined SRAM output data is temporarily stored by the edge triggered output register during the access cycle and then released to the output drivers at the next rising edge of clock ...
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DDQ ...
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DQP DDQ ...
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TQFP Pin Descriptions Symbol Type ...
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... GS880Z18/36B NBT SRAM Functional Block Diagram Rev: 1.02 10/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS880Z18/36BT-333/300/250/200/150 Amps Sense Drivers Write 5/24 © 2001, GSI Technology ...
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... A B cycle with no Byte Write inputs active is a no-op cycle. The pipelined NBT SRAM provides double late write functionality, matching the write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At the first rising edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is required at the third rising edge of clock ...
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... Dummy Read and Write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs when the W pin is sampled low but no Byte Write pins are active so no write operation is performed can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during write cycles. 4. ...
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Pipeline and Flow Through Read Write Control State Diagram New Read R R Burst Read B Key Input Command Code ƒ Transition Current State (n) Next State (n+1) n Clock (CK) Command Current State Current State and Next State Definition ...
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Intermediate B W High Z (Data In) Key Input Command Code ƒ Transition Current State (n) Intermediate State (N+1) Clock (CK) Command Current State and Next State Definition for Rev: 1.02 10/2004 Specifications cited are subject to change without notice. ...
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B W High Z (Data In) Key Input Command Code ƒ Transition Current State (n) Clock (CK) Command Current State and Next State Definition for: Rev: 1.02 10/2004 Specifications cited are subject to change without notice. For latest documentation see ...
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... SRAM to advance the internal address counter and use the counter generated address to read or write the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into Load mode ...
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... During normal operation, ZZ must be pulled low, either by the user or by it’s internal pull down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates normally after ZZ recovery time. ...
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Absolute Maximum Ratings (All voltages reference Symbol DDQ V I/O V Voltage on Other Input Pins IN I Input Current on Any Pin IN I Output Current on Any I/O Pin OUT P ...
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V Range Logic Levels DDQ3 Parameter V Input High Voltage DD V Input Low Voltage DD V I/O Input High Voltage DDQ V I/O Input Low Voltage DDQ Notes: 1. The part numbers of Industrial Temperature Range versions end the ...
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Undershoot Measurement and Timing 50% V – 2 50% tKC Capacitance 2 Parameter Input Capacitance Input/Output Capacitance Note: ...
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DC Electrical Characteristics Parameter Input Leakage Current (except mode pins) ZZ Input Current FT, SCD, ZQ Input Current Output Leakage Current Output High Voltage Output High Voltage Output Low Voltage Rev: 1.02 10/2004 Specifications cited are subject to change without ...
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Operating Currents Parameter Test Conditions (x32/ x36) Device Selected; All other inputs Operating ≥V or ≤ V Current IH IL Output open (x18) Standby ZZ ≥ V – 0.2 V — DD Current Device Deselected; Deselect All other inputs — ...
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AC Electrical Characteristics Parameter Clock Cycle Time Clock to Output Valid Clock to Output Invalid Pipeline Clock to Output in Low-Z Setup time Hold time Clock Cycle Time Clock to Output Valid Clock to Output Invalid Flow Through Clock to ...
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Write A Write CKE ADV A0– DQa–DQd G *Note: E=High(False ...
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Write A Write CKE ADV A0– D(A) G *Note High(False ...
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TQFP Package Drawing (Package T) Symbol Description Min. Nom. Max A1 Standoff 0.05 A2 Body Thickness 1.35 b Lead Width 0.20 c Lead Thickness 0.09 D Terminal Dimension 21.9 D1 Package Body 19.9 E Terminal Dimension 15.9 E1 Package Body ...
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... GS880Z36BT-200I 256K x 36 GS880Z36BT-150I 512K x 18 GS880Z18BGT-333 512K x 18 GS880Z18BGT-300 512K x 18 GS880Z18BGT-250 512K x 18 GS880Z18BGT-200 512K x 18 GS880Z18BGT-150 256K x 36 GS880Z36BGT-333 256K x 36 GS880Z36BGT-300 256K x 36 GS880Z36BGT-250 256K x 36 GS880Z36BGT-200 256K x 36 GS880Z36BGT-150 Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: Gs880Z18BT-150IT. ...
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... Ordering Information—GSI NBT Synchronous SRAM 1 Org Part Number 512K x 18 GS880Z18BGT-333I 512K x 18 GS880Z18BGT-300I 512K x 18 GS880Z18BGT-250I 512K x 18 GS880Z18BGT-200I 512K x 18 GS880Z18BGT-150I 256K x 36 GS880Z36BGT-333I 256K x 36 GS880Z36BGT-300I 256K x 36 GS880Z36BGT-250I 256K x 36 GS880Z36BGT-200I 256K x 36 GS880Z36BGT-150I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: Gs880Z18BT-150IT. ...
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... Sync SRAM Data Sheet Revision History DS/DateRev. Code: Old; Types of Changes New Format or Content 880Z18B_r1 880Z18B_r1; 880Z18B_r1_01 880Z18B_r1_01; 880Z18B_r1_02 Rev: 1.02 10/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Page;Revisions;Reason • Creation of new datasheet • Removed address and DQ number designations • ...