GS8321E18E GSI [GSI Technology], GS8321E18E Datasheet - Page 8

• Manufacturer Part Number: GS8321E18E
• Description: 2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs
• Manufacturer: GSI [GSI Technology]

Mode Pin Functions
Note:
There are pull-up devices on the FT pin and a pull-down device on the ZZ pin, so those input pins can be unconnected and the
chip will operate in the default states as specified in the above tables.
Burst Counter Sequences
Linear Burst Sequence
Note:
The burst counter wraps to initial state on the 5th clock.
Rev: 1.03 4/2005
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
2nd address
3rd address
4th address
1st address
Output Register Control
Power Down Control
Burst Order Control
Mode Name
A[1:0] A[1:0] A[1:0] A[1:0]
00
01
10
11
01
11
00
10
Name
10
11
00
01
LBO
Pin
ZZ
FT
11
00
01
10
H or NC
L or NC
State
H
H
L
L
8/34
Standby, I
I
Note:
The burst counter wraps to initial state on the 5th clock.
Interleaved Burst
nterleaved Burst Sequence
Flow Through
Linear Burst
Function
2nd address
3rd address
4th address
1st address
Pipeline
GS8321E18/32/36E-250/225/200/166/150/133
Active
DD
= I
SB
A[1:0] A[1:0] A[1:0] A[1:0]
00
01
10
11
01
00
11
10
10
11
00
01
© 2003, GSI Technology
11
10
01
00
BPR 1999.05.18