GS8644ZV18B-150I GSI [GSI Technology], GS8644ZV18B-150I Datasheet
GS8644ZV18B-150I
Related parts for GS8644ZV18B-150I
GS8644ZV18B-150I Summary of contents
Page 1
... The GS8644ZV18/36/ 72Mbit Synchronous Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other pipelined read/double late write or flow through read/ single late write SRAMs, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles. ...
Page 2
GS8644ZV72C Pad Out—209-Bump BGA—Top View (Package DQP DQP G ...
Page 3
GS8644ZV72 209-Bump BGA Pin Description Symbol Type I ...
Page 4
GS8644ZV72 209-Bump BGA Pin Description (Continued) Symbol Type I TMS I TDI O TDO I TCK DDQ Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see ...
Page 5
GS8644ZV36B Pad Out—119-Bump BGA—Top View (Package DDQ DQC E DQC V F DDQ G DQC H DQC V J DDQ K DQD L DQD V M DDQ N DQD P DQD ...
Page 6
... GS8644ZV18B Pad Out—119-Bump BGA—Top View (Package DDQ DQB DDQ DQB V J DDQ DQB V M DDQ N DQB DDQ Bump BGA— Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. ...
Page 7
GS8644ZV18/36 119-Bump BGA Pin Description Symbol Type I — ...
Page 8
Bump BGA—x18 Common I/O—Top View (Package DDQ D NC DQB V DDQ E NC DQB V DDQ F NC DQB V DDQ G ...
Page 9
Bump BGA—x36 Common I/O—Top View (Package DQPC NC V DDQ D DQC DQC V DDQ E DQC DQC V DDQ F DQC DQC V DDQ G ...
Page 10
GS8644ZV18/36E 165-Bump BGA Pin Description Symbol Type I — ...
Page 11
... A B cycle with no Byte Write inputs active is a no-op cycle. The pipelined NBT SRAM provides double late write functionality, matching the write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At the first rising edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is required at the third rising edge of clock ...
Page 12
... Dummy Read and Write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs when the W pin is sampled low but no Byte Write pins are active so no write operation is performed can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during write cycles. 4. ...
Page 13
Pipelined and Flow Through Read Write Control State Diagram New Read R R Burst Read B Key Input Command Code ƒ Transition Current State (n) Next State (n+1) n Clock (CK) Command Current State Current State and Next State Definition ...
Page 14
Intermediate B W High Z (Data In) Key Input Command Code ƒ Transition Current State (n) Intermediate State (N+1) Clock (CK) Command Current State and Next State Definition for Rev: 1.03 11/2004 Specifications cited are subject to change without notice. ...
Page 15
B W High Z (Data In) Key Input Command Code ƒ Transition Current State (n) Clock (CK) Command Current State and Next State Definition for: Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see ...
Page 16
... SRAM to advance the internal address counter and use the counter generated address to read or write the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into Load mode ...
Page 17
... During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates normally after 2 cycles of wake up time. ...
Page 18
Absolute Maximum Ratings (All voltages reference Symbol DDQ V I/O V Voltage on Other Input Pins IN I Input Current on Any Pin IN I Output Current on Any I/O Pin OUT P ...
Page 19
V Range Logic Levels DDQ Parameter V Input High Voltage DD V Input Low Voltage DD V I/O Input High Voltage DDQ V I/O Input Low Voltage DDQ Notes: 1. The part numbers of Industrial Temperature Range versions end the ...
Page 20
AC Test Conditions Parameter Input high level Input low level Input slew rate Input reference level Output reference level Output load Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. ...
Page 21
Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8644ZV18(B/E)/GS8644ZV36(B/E)/GS8644ZV72(C) 21/37 Product Preview © 2003, GSI Technology ...
Page 22
AC Electrical Characteristics Parameter Symbol Clock Cycle Time Clock to Output Valid (x18/x36) Clock to Output Valid (x72) Pipeline Clock to Output Invalid Clock to Output in Low-Z Setup time Hold time Clock Cycle Time Clock to Output Valid Clock ...
Page 23
Write A Read CKE ADV Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation ...
Page 24
Write A Write CKE ADV A0– D(A) G *Note High(False ...
Page 25
Disabling the JTAG Port It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal ...
Page 26
Boundary Scan Register · · 0 Bypass Register Instruction Register TDI ID Code Register · · · · Control Signals · TMS · Test Access Port (TAP) Controller TCK ...
Page 27
Test Logic Reset 1 0 Run Test Idle 0 Instruction Descriptions BYPASS When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This occurs when the TAP controller is moved to ...
Page 28
EXTEST EXTEST is an IEEE 1149.1 mandatory public instruction executed whenever the instruction register is loaded with all logic 0s. The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal ...
Page 29
JTAG Port AC Test Conditions Parameter Input high level Input low level Input slew rate Input reference level Output reference level Notes: 1. Include scope and jig capacitance. 2. Test conditions as as shown unless otherwise noted. JTAG TAP Instruction ...
Page 30
... OLJ –100 uA OHJC +100 uA OHJC TCK TDI TMS TDO Parallel SRAM input Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8644ZV18(B/E)/GS8644ZV36(B/E)/GS8644ZV72(C) Symbol V IHJ V ILJ I INHJ I INLJ I OLJ V OHJ ...
Page 31
JTAG Port AC Electrical Characteristics Parameter Symbol TCK Cycle Time tTKC TCK Low to TDO Valid tTKQ TCK High Pulse Width tTKH TCK Low Pulse Width tTKL TDI & TMS Set Up Time tTS TDI & TMS Hold Time tTH ...
Page 32
Body, 1.0 mm Bump Pitch Bump Array A aaa e Symbol Min Typ A — — A1 0.40 0.50 ∅b 0.50 0.60 c 0.31 0.36 D 21.9 22.0 Rev 1.0 Rev: 1.03 ...
Page 33
Package Dimensions—165-Bump FPBGA (Package E; Variation 1) A1 TOP VIEW SEATING PLANE C ...
Page 34
Package Dimensions—119-Bump FPBGA (Package B, Variation 2 TOP VIEW SEATING PLANE C Rev: 1.03 11/2004 ...
Page 35
... GS8644ZV72C-133 Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8644ZV18B-150IB. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user ...
Page 36
... GS8644ZV72C-133I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8644ZV18B-150IB. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user ...
Page 37
... Sync SRAM Datasheet Revision History Types of Changes DS/DateRev. Code: Old; Format or Content New 8644ZVxx_r1 8644ZVxx_r1; 8644ZVxx_r1_01 8644ZVxx_r1_01; 8644ZVxx_r1_02 8644ZVxx_r1_02; 8644ZVxx_r1_03 Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8644ZV18(B/E)/GS8644ZV36(B/E)/GS8644ZV72(C) Page;Revisions;Reason • Creation of new datasheet • ...