GS8322Z18 GSI [GSI Technology], GS8322Z18 Datasheet
GS8322Z18
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GS8322Z18 Summary of contents
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... This feature eliminates complex off- chip write pulse generation required by asynchronous SRAMs and simplifies input signal timing. The GS8322Z18/36/72 may be configured by the user to operate in Pipeline or Flow Through mode. Operating as a pipelined synchronous device, in addition to the rising-edge- triggered registers that capture input signals, the device incorporates a rising edge triggered output register ...
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... TMS D D Rev: 1.04 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72( ADV ...
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... CKE Rev: 1.04 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C) Description Address field LSBs and Address Counter Preset Inputs Address Inputs Data Input and Output pins Byte Write Enable for I/Os ...
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... DDQ Rev: 1.04 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C) Description Scan Test Mode Select Scan Test Data In Scan Test Data Out Scan Test Clock Core power supply I/O and Core Ground ...
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... DQD V M DDQ N DQD P DQD DDQ Bump BGA— Rev: 1.04 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72( ADV ...
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... GS8322Z18B Pad Out—119-Bump BGA—Top View (Package DDQ DQB DDQ DQB V J DDQ DQB V M DDQ N DQB DDQ Bump BGA— Rev: 1.04 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. ...
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... GS8322Z18/36 119-Bump BGA Pin Description Symbol Type I — CKE ADV LBO TMS I TDI TDO O I TCK ...
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... NC V DDQ LBO Bump BGA— Body—1.0 mm Bump Pitch Rev: 1.04 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72( CKE ADV ...
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... NC V DDQ LBO Bump BGA— Body—1.0 mm Bump Pitch Rev: 1.04 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72( CKE ADV ...
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... GS8322Z18/36E 165-Bump BGA Pin Description Symbol Type I — CKE ADV LBO I I TMS I TDI O TDO I TCK — ...
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... Rev: 1.04 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72( ...
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... This device contains circuitry that ensures all outputs are in High Z during power-up 2-bit burst counter is incorporated. 10. The address counter is incriminated for all Burst continue cycles. Rev: 1.04 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C) External L ...
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... Input Command Code ƒ Transition Current State (n) Next State (n+1) n Clock (CK) Command Current State Current State and Next State Definition for Rev: 1.04 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72( Deselect ...
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... Transition Current State (n) Intermediate State (N+1) Clock (CK) Command Current State and Next State Definition for Rev: 1.04 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C) Pipeline Mode Data I/O State Diagram Intermediate R D Intermediate Intermediate W ...
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... Transition Current State (n) Clock (CK) Command Current State and Next State Definition for: Rev: 1.04 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C) Flow Through Mode Data I/O State Diagram High ...
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... Note: The burst counter wraps to initial state on the 5th clock. Rev: 1.04 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C) Pin State Function Name L Linear Burst LBO H Interleaved Burst ...
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... GSI RAM is fully compatible with these sockets. In the unlikely event the part being replaced is a Flow Through device, the pin will need to be pulled low for correct operation. Rev: 1.04 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C) Sleep Mode Timing Diagram tKH tKH ...
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... Input Under/overshoot voltage must be –2 V > Vi < V Rev: 1.04 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C) Description Voltage on V Pins DD ...
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... Input Under/overshoot voltage must be –2 V > Vi < V Rev: 1.04 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C) Symbol Min. Typ. V 2.0 — ...
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... Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted. 3. Device is deselected as defined by the Truth Table. DQ Rev: 1.04 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C) Overshoot Measurement and Timing 50% V ...
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... Output Leakage Current (x36/x72) Output Leakage Current (x18) Output High Voltage Output High Voltage Output Low Voltage Rev: 1.04 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C) Symbol Test Conditions ≥ ...
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... Rev: 1.04 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C) 22/38 © 2002, GSI Technology ...
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... asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold times as specified above. Rev: 1.04 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C) -250 -225 Min ...
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... A0– DQa–DQd G *Note: E=High(False Rev: 1.04 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C) Pipeline Mode Timing (NBT) Write B+1 Read C Cont Read D tKL tKL tKH tKH ...
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... TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG Port unused, TCK, TDI, and TMS may be left floating or tied to either V Rev: 1.04 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C) Flow Through Mode Timing (NBT) Write B+1 Read C ...
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... Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z, SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register. Rev: 1.04 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C) Description 26/38 © 2002, GSI Technology ...
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... Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins. Rev: 1.04 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C) JTAG TAP Block Diagram · ...
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... TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this device is listed in the following table. Rev: 1.04 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C) Not Used Configuration 0 ...
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... The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is still determined by its input pins. Rev: 1.04 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C) JTAG Tap Controller State Diagram 1 1 ...
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... Places Bypass Register between TDI and TDO. Notes: 1. Instruction codes expressed in binary, MSB on left, LSB on right. 2. Default instruction automatically loaded at power-up and in test-logic-reset state. Rev: 1.04 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C) Description 30/38 Notes ...
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... Input reference level Output reference level Notes: 1. Include scope and jig capacitance. 2. Test conditions as shown unless otherwise noted. Rev: 1.04 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C) Symbol V IHJ3 V ILJ3 V IHJ2 V ILJ2 ...
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... For information regarding the Boundary Scan Chain obtain BSDL files for this part, please contact our Applications Engineering Department at: apps@gsitechnology.com. Rev: 1.04 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C) JTAG Port Timing Diagram tTKC tTKC ...
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... A A1 0.40 0.50 ∅b 0.50 0.60 c 0.31 0.36 D 21.9 22.0 D1 18.0 (BSC) E 13.9 14.0 E1 10.0 (BSC) e 1.00 (BSC) aaa 0.15 Rev 1.0 Rev: 1.04 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72( ∅b e Max Units 1.70 mm 0.60 mm 0.70 mm 0. 33/ Side View Bottom View ...
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... SEATING PLANE C Rev: 1.04 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C) BOTTOM VIEW Ø0. Ø0. Ø0.44~0.64(165x 1.0 10.0 15±0. ...
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... SEATING PLANE C Rev: 1.04 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C) BOTTOM VIEW A1 Ø0. Ø0. Ø0.60~0.90 (119x 7.62 14±0. ...
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... GS8322Z72C-133 Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8322Z18B-150IB. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user ...
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... GS8322Z72C-133I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8322Z18B-150IB. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user ...
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... Rev: 1.04 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C) Page;Revisions;Reason • Creation of new datasheet • Add 165 BGA C • Fix missing address at B9 and ZQ at H10 in 165 pinouts C • ...