SCD1283 INTEL [Intel Corporation], SCD1283 Datasheet - Page 42

• Manufacturer Part Number: SCD1283
• Description: IEEE 1284-Compatible Parallel Interface
• Manufacturer: INTEL [Intel Corporation]

CD1283 — IEEE 1284-Compatible Parallel Interface
5.8
5.9
42
Table 7.
Note: Interrupts are not generated on signal changes within the General-Purpose I/O port; the CPU must
System Clock Setup
General-Purpose I/O Port
The CD1283 provides an 8-bit general-purpose port (GP[7:0]) used to control or give status of
external functions. Each of the eight signals are individually programmable for direction, so the
port can be comprised of any number of inputs and outputs. Each port signal is implemented with a
standard, bidirectional HCMOS pad and is fully TTL compatible. The port is controlled through
two internal registers — GPDIR and GPIO.
Each bit in the GPDIR sets the direction of the corresponding bit in the GPIO; ‘1’ sets the signal as
output, and ‘0’ sets it as input. When writing to the GPIO, only the bits programmed as outputs are
affected by the contents of the data bus. When reading the GPIO, bits programmed as inputs reflect
the true state of the condition of the external pin; bits programmed as outputs reflect the state of the
last value written to the register and the current state of the output pins.
At reset, all bits in the GPIO are cleared and the signals are programmed as inputs.
periodically poll GPIO to detect changes in external conditions. Therefore, if it is necessary to
detect changes, use the port with signals that change with low-duty cycles.
Parallel Port Interface
The CD1283 parallel port signals are implemented with Level-2 characteristics, as defined in the
IEEE Std 1284-1994 specification with the exception of transient protection. As such, the port can
be directly connected to the interface cable with the addition of a few external components. The
components consist of passive pull-up resistors, series impedance matching resistors, and clipping
diodes. Additional noise filtering may be required in an end system.
interface with the components listed above.
Some system designs may require buffers between the CD1283 and the cable. Systems that require
drive cables longer than the specified maximum of 10 m or those that need to protect the CD1283
require inexpensive buffers between it and the cable. The device provides two signal outputs,
PDBEN and EBDIR, for connecting and controlling buffers (such as, 74AS245 or equivalent).
These signals do not allow direct control of the buffer. However, the addition of an XNOR gate
provides both an enable control signal and a signal to select the direction of the buffer. PDBEN and
EBDIR are outputs from the control state machine that indicate its current state (see
page
CLK Freq.
(MHz)
44).
16
20
25
Time/Tic
(ns)
62.5
50
40
SPR Value
10
13
8
T
P
500
500
520
Width
Figure 10
illustrates a typical
Figure 11 on
Datasheet