SCD1283 INTEL [Intel Corporation], SCD1283 Datasheet - Page 79

• Manufacturer Part Number: SCD1283
• Description: IEEE 1284-Compatible Parallel Interface
• Manufacturer: INTEL [Intel Corporation]

Datasheet
NOTES:
CLK/2
RESET*
1. Timing numbers for RESET* and CLK are valid for both asynchronous and synchronous specifications. The device will
2. On host-I/O cycles, immediately following SVCACK* cycles and writes to EOSRR, DTACK* will be delayed by 20 CLKs (1 ms
3. As TCLK increases, device performance decreases. A minimum clock frequency of 25 MHz is required to guarantee specified
4. DTACK* sources current (drives ‘high’) until the voltage on the DTACK* line is approximately 1.5 V; then DTACK* goes to the
Timing
No.
t
t
t
t
t
t
t
operate on any clock with a 40–60 or better duty cycle.
@ 20 MHz; 800 ns @ 25 MHz). On systems that do not use DTACK* to signal the end of the I/O cycle, wait states or some
other form of delay generation must be used to assure that the CD1283 is not accessed until after this time period.
performance. The recommended maximum TCLK is 1000 ns.
‘open-drain’ (high-impedance) state.
CLK
Table 12. Asynchronous Timing Reference Parameters (Sheet 2 of 2)
25
26
27
28
29
30
31
Figure 17. Reset Timing
V
CC
Note: For synchronous systems, it is necessary to determine the clock cycle number so that interface
Figure
23
23
23
23
25
23
25
25
25
circuitry can stay in lock-step with the device. CLK numbers can be determined if RESET* is
released within the range t
is defined as 5 ns minimum, before the next rising edge of the clock. If these conditions are met, the
cycle starting after the second rising edge will be C1. See the synchronous timing diagrams for
additional information. Clock numbers are not important in asynchronous systems.
The following timing numbers are for the back-to-back asynchronous DMA timing diagrams.
Hold time, DMAACK* active (DMA read/write)
Delay, data valid after falling edge DMAACK* (DMA read)
Hold time, data valid after rising edge DMAACK* (DMA read)
Inactive time, DMAACK* (DMA read/write)
Hold time, DMAREQ* rising edge after
DMAACK* falling edge (DMA read/write)
Hold time, DMAACK* active (DMA write)
Delay, data valid after falling edge DMAACK* (DMA write)
t
1
a
Parameter
–t
b
; t
a
is defined as 10 ns minimum, after the rising edge of the clock; t
IEEE 1284-Compatible Parallel Interface — CD1283
t
a
t
b
C2
0.5 CLK
2.5 CLK
C1
3 CLK
MIN
10
10
10
20
C2
1.5 CLK
1 CLK
1.5 CLK
MAX
C1
30
15
25
C2
Unit
ns
ns
ns
ns
79
b