SCD1284 INTEL [Intel Corporation], SCD1284 Datasheet - Page 147

• Manufacturer Part Number: SCD1284
• Description: IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports
• Manufacturer: INTEL [Intel Corporation]

7.8.3
Datasheet
Register Name: IVR
Register Description: Input Value
Access: Read only
Bit 7
0
7:4
Bit
3
2
1
0
14-bit counter is started (from 0x00). It counts up until either the expected event occurs or the
count matches the value in HTVR. If a match occurs, a timeout condition exists. The HTVR need
only be loaded once, typically during device initialization.
The value placed in HTVR yields an approximate one second count time, based on the value of the
input CLK. For example, if the system clock driving the device is 25 MHz, the HTVR should be
loaded with 0xC0. The following equation provides an example.
The computed value is rounded up to the next largest whole hex value, in this case ‘0x3000’. Load
the HTVR with the most-significant 8 bits of this value, left-shifted two places since HTVR is a 14-
bit counter. This results in a value of ‘0xC0’. For 20 MHz, the value is computed to be ‘0x9C’; for
16 MHz, the value is ‘0x7C’; values for other clocks can be easily computed in the same manner.
At reset, the HTVR defaults to a value of ‘0xFF’; this prevents the extremely short timeouts that
occur if the register is cleared at device reset and is not initialized.
A timeout causes a negotiation status change interrupt. This status is displayed as ‘0x22’ in the
NSR (NSR[5] and the code for return to Compatibility mode – ‘0010’ – in the result code field).
When Compatibility mode is reentered, the port control state machine waits in a locked state until
signals on the parallel port return to normal Compatibility mode conditions.
For debug purposes, disable the host timeout timer by setting PCR[3:2] (HTmrTst[1:0]). In this
case, no timeouts occur and the link can hang indefinitely while waiting for a host-generated event.
Input Value Register
This register always shows the current state of the external handshake pins.
These bits are not used and return ‘0’ when read.
A1284
nInit (low active Init input)
HstBsy (host busy)
HstClk (host clock)
Bit 6
0
Bit 5
0
IEEE 1284-Compatible Parallel Interface Controller — CD1284
25MHz
----------------- -
2048
Bit 4
0
=
Description
12207
A1284
Bit 3
10
=
2FAF
Bit 2
nInit
16
HstBsy
Bit 1
8-Bit Hex Address: 2E
Default Value: XX
HstClk
Bit 0
147