SCD1284 INTEL [Intel Corporation], SCD1284 Datasheet - Page 162

• Manufacturer Part Number: SCD1284
• Description: IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports
• Manufacturer: INTEL [Intel Corporation]

CD1284 — IEEE 1284-Compatible Parallel Interface Controller
162
DMAACK*
DMAREQ*
DMAREQ*
DMAACK*
DB[15:0]
DB[15:0]
NOTE: The falling edge of DMAACK* is synchronized internally with the rising edge of the clock when asynchronous
NOTES:
NOTES:
1. The DMA handshake operates in asynchronous mode only if the AsyncDMA bit is set in PACR.
1. The DMA handshake operates in asynchronous mode only if the AsyncDMA bit is set in PACR.
2. If DMAACK* is released after point ‘a,’ but before point ‘b’ (two rising CLK edges after the falling edge of
2. If DMAACK* is released after point ‘a,’ but before point ‘b’ (two rising CLK edges after the falling edge of DMAACK*),
3. Figure 25 is still valid, however, Figure 26 illustrates more robust timing.
3.
Figure 25. Asynchronous DMA Read Cycle Timing
Figure 26. Asynchronous DMA Read Cycle Timing (Two Back-to-Back DMA Reads)
CLK
DMAACK*), DB[15:0] is released at t
DB[15:0] is released at t
controls the release of DB[15:0]; the data bus remains active until DMAACK* becomes inactive (point ‘c’).
DB[15:0]; the data bus remains active until DMAACK* becomes inactive (point ‘c’).
Figure 25
CLK
timing is selected by PACR[1]. The data valid time can vary by as much as one full CLK cycle depending on when
DMAACK* falling edge occurs in relation to the CLK rising edge. The minimum DMAACK* active time must be met
to ensure that the data has become valid before the rising edge of DMAACK*. The DMAACK* can be extended to
any length, which extends the data valid hold time accordingly. If t
than t
is still valid, however,
25
(MIN), then the data bus tristates t
20
following the rising edge of CLK. If DMAACK* is held past this edge, it controls the release of
DMAACK* SYNCHRONIZED
Figure 26
20
HERE
following the rising edge of CLK. If DMAACK* is held past this edge, it
t
t
illustrates more robust timing.
19
SEE NOTE
24
t
26
27
t
25
after the third rising clock edge following the assertion of DMAACK*.
t
23
VALID
‘a’
25
MAY CHANGE
t
28
is not met and DMAACK* is deasserted in less
t
27
VALID
t
29
SEE NOTE
‘b’
t
20
VALID
Datasheet
‘c’