PPC440GRX-NPAFFFTS AMCC [Applied Micro Circuits Corporation], PPC440GRX-NPAFFFTS Datasheet
PPC440GRX-NPAFFFTS
Related parts for PPC440GRX-NPAFFFTS
PPC440GRX-NPAFFFTS Summary of contents
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... JTAG interface for board level testing. • Boot from PCI memory, NOR Flash on the external peripheral bus, or NAND Flash on the NAND Flash interface. • Optional security feature (PPC440GRx-S). • Available in RoHS compliant, lead-free package. Technology: CMOS Cu-11, 0.13μm. Package: 35mm, 680-ball thermally enhanced plastic ball grid array (TE-PBGA) ...
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... PPC440GRx Embedded Processor Contents Ordering and PVR Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Address Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 PowerPC 440 Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 SRAM Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Internal Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Security Function (optional KASUMI Algorithm (optional PCI Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 DDR2/1 SDRAM Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 External Peripheral Bus Controller (EBC Ethernet Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 DMA-to-PLB3 (64-bit) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Serial Ports (UART) ...
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... Revision 1.08 – October 15, 2007 Preliminary Data Sheet Figures Figure 1. Order Part Number Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 2. PPC440GRx Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 3. 35mm, 680-Ball TE-PBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 4. Overshoot Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Figure 5. Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Figure 6. Input Setup and Hold Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Figure 7. Output Delay and Float Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Figure 8 ...
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... PPC440GRx Embedded Processor Table 27. I/O Timing—DDR SDRAM T Table 28. Strapping Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 4 and Revision 1.08 – October 15, 2007 Preliminary Data Sheet AMCC Proprietary ...
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... Product Name (see Notes) PPC440GRx PPC440GRx-SpAfffTs PPC440GRx PPC440GRx-NpAfffTs Notes: Characters following the dash (-): Security feature present Security feature not present Package type lead-free (RoHS compliant contains lead Chip revision level A 4. fff = Processor frequency: 400 = 400MHz, 533 = 533MHz, 667 = 667MHz Case temperature range of − ...
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... PLB (PLB4—128 bits) DMA Controller DDR2/1 SDRAM Controller 333MHz max data rate - 14-bit addr - 64/32-bit data The PPC440GRx is a system on a chip (SOC) using IBM CoreConnect Bus 6 Power Mgmt 83MHz max DCRs - 30-bit addr - 32/16-bit data DCR Bus Trace 32KB ...
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... Preliminary Data Sheet Address Maps The PPC440GRx incorporates two address maps. The first is a fixed processor System Memory Address Map. This address map defines the possible contents of various address regions which the processor can access. The second is the DCR Address Map for Device Configuration Registers (DCRs). The DCRs are accessed by software running on the PPC440GRx processor through the use of mtdcr and mfdcr instructions ...
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... PPC440GRx Embedded Processor Table 1. System Memory Address Map (Sheet Function Internal Peripherals 1 EBC Boot space Notes: 1. EBC and PCI are relocatable, but this map reflects the suggested configuration. 8 Sub Function Start Address Reserved 1 EF50 0000 General Purpose Timer ...
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... On Chip Memory (SRAM Controller) Reserved Notes: 1. DCR addresses are 10 bits (1024 or 1K unique addresses). Each unique address represents a single 32-bit (word) register. One kiloword (1024W) equals 4KB (4096 B). AMCC Proprietary 440GRx – PPC440GRx Embedded Processor Start Address End Address 000 3FF 000 ...
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... PPC440GRx Embedded Processor PowerPC 440 Processor The PowerPC 440 processor is designed for high-end applications: RAID controllers, SAN, iSCSI, routers, switches, printers, set-top boxes, etc. It implements the Book E PowerPC embedded architecture and uses the 128-bit version of IBM’s on-chip CoreConnect Bus Architecture. ...
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... DCR – 32-bit data path – 10-bit address Security Function (optional) The built-in security function (PPC440GRx-S only cryptographic engine attached to the 128-bit PLB with built- in DMA and interrupt controllers. Features include: • Federal Information Processing Standard (FIPS) 140-2 design • ...
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... PPC440GRx Embedded Processor • Public key acceleration for RSA, DSA and Diffie-Hellman • True or pseudo random number generators – Non-deterministic true random numbers – Pseudo random numbers with lengths 16B – ANSI X9.17 Annex C compliant using a DES algorithm • Interrupt controller – ...
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... Write posting from external master – Read prefetching on PLB for external master reads – Bursting capable from external master – Allows external master access to all non-EBC PLB slaves – External master can control EBC slaves for access AMCC Proprietary 440GRx – PPC440GRx Embedded Processor 13 ...
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... PPC440GRx Embedded Processor Ethernet Controller Ethernet support provided by the PPC440GRx interfaces to the physical layer but the PHY is not included on the chip: • Two 10/100/1000 interfaces running in full- and half-duplex modes providing: – One Gigabit Media Independent Interface (GMII) – One Media Independent Interface (MII) – ...
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... Execute up to 4KB of boot code out of first block. – Automatic page read accesses performed based on device configuration and addressing mode. • ECC provides single-bit error correction and double-bit error detection in each 256B of stored data AMCC Proprietary 440GRx – PPC440GRx Embedded Processor 2 C Specification, dated 1995 15 ...
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... PPC440GRx Embedded Processor General Purpose Timers (GPT) Provides a separate time base counter and additional system timers in addition to those defined in the processor. Features include: • 32-bit Time Base Counter driven by the OPB bus clock • Seven 32-bit compare timers General Purpose IO (GPIO) Controller • ...
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... 680 x 0.60 ± 0.10 Solder Ball Notes: AMCC Proprietary 440GRx – PPC440GRx Embedded Processor ® PPC440GRx e1 PPC440GRx-nprffft ccccccc 1YWWBZZZZZ Lot Number (ZZZZZ) 35.0 33.0 Thermal Balls 9 ...
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... PPC440GRx Embedded Processor Assembly Recommendations Table 3. Recommended Reflow Soldering Profile Profile Feature Average ramp-up rate Preheat • Temperature Min • Temperature Max • Time (min to max) Time Maintained Above: • Temperature • Time Peak Temperature Time within 5°C of Actual Peak Temperature Ramp-down Rate Time 25° ...
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... DM5 DM6 DM7 DM8 [DMAAck0][IRQ8]GPIO47 [DMAAck1][IRQ4]GPIO44 [DMAAck2][PerAddr06]GPIO01 [DMAAck3][PerAddr03]GPIO04 [DMAReq0][IRQ7]GPIO46 [DMAReq1]IRQ5[ModeCtrl] [DMAReq2][PerAddr07]GPIO00 [DMAReq3][PerAddr04]GPIO03 AMCC Proprietary 440GRx – PPC440GRx Embedded Processor Ball Interface Group AP25 Power AP24 AJ03 AK03 DDR SDRAM AP08 AH02 DDR SDRAM AH01 ...
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... PPC440GRx Embedded Processor Table 5. Signals Listed Alphabetically (Sheet 2 of 26) Signal Name DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8 DrvrInh1 [DrvrInh2]Halt EAGND EAV DD ECC0 ECC1 ECC2 ECC3 ECC4 ECC5 ECC6 ECC7 [EOT0/TC0][IRQ9]GPIO48 [EOT1/TC1][IRQ6]GPIO45 [EOT2/TC2][PerAddr05]GPIO02 [EOT3/TC3][PerAddr02]GPIO05 ...
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... GMC0TxD2] GPIO24 [GMCTxD3, GMC0TxD3] GPIO25 [GMCTxD4, GMC1TxD0] GPIO16 [GMCTxD5, GMC1TxD1] GPIO17 [GMCTxD6, GMC1TxD2] GPIO18 [GMCTxD7, GMC1TxD3] GPIO19 GMCTxEr, GMC1TxCtl GMCTxEn, GMC0TxCtl AMCC Proprietary 440GRx – PPC440GRx Embedded Processor Ball Interface Group A04 External Master Peripheral D06 External Master Peripheral AJ32 AK32 ...
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... PPC440GRx Embedded Processor Table 5. Signals Listed Alphabetically (Sheet 4 of 26) Signal Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND ...
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... GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND AMCC Proprietary 440GRx – PPC440GRx Embedded Processor Ball Interface Group E16 E18 E19 E25 E27 E30 E31 H01 H02 H05 H30 H33 K01 K04 K05 ...
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... PPC440GRx Embedded Processor Table 5. Signals Listed Alphabetically (Sheet 6 of 26) Signal Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND ...
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... GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND AMCC Proprietary 440GRx – PPC440GRx Embedded Processor Ball Interface Group V30 W02 W05 W15 W16 W17 W18 W19 W20 W30 W33 Y13 Y14 Y15 Y16 ...
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... PPC440GRx Embedded Processor Table 5. Signals Listed Alphabetically (Sheet 8 of 26) Signal Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND ...
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... Table 5. Signals Listed Alphabetically (Sheet 9 of 26) Signal Name GND GND GND GND GND GND GND GND GND GND GND GND AMCC Proprietary 440GRx – PPC440GRx Embedded Processor Ball Interface Group AN19 AN27 AN31 AN32 AN33 AN34 Power AP01 AP02 AP03 AP32 AP33 ...
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... PPC440GRx Embedded Processor Table 5. Signals Listed Alphabetically (Sheet 10 of 26) Signal Name GPIO00[PerAddr07][DMAReq2] GPIO01[PerAddr06][DMAAck2] GPIO02[PerAddr05][EOT2/TC2] GPIO03[PerAddr04][DMAReq3] GPIO04[PerAddr03][DMAAck3] GPIO05[PerAddr02][EOT3/TC3] GPIO06[PerCS1][NFCE1] GPIO07[PerCS2][NFCE2] GPIO08[PerCS3][NFCE3] GPIO09[PerCS4] GPIO10[PerCS5] GPIO11[PerErr] GPIO12[NFREn] GPIO13[NFWEn] GPIO14[NFCLE] GPIO15[NFALE] GPIO16[GMCTxD4, GMC1TxD0] GPIO17[GMCTxD5, GMC1TxD1] ...
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... GPIO54[TrcES2] GPIO55[TrcES3] GPIO56[TrcES4] GPIO57[TrcTS0] GPIO58[TrcTS1] GPIO59[TrcTS2] GPIO60[TrcTS3] GPIO61[TrcTS4] GPIO62[TrcTS5] GPIO63[TrcTS6] Halt[DrvrInh2] [HoldAck]GPIO29 HoldPri[LeakTest] HoldReq[RcvrInh] IIC0SClk IIC0SData[GPIO26] AMCC Proprietary 440GRx – PPC440GRx Embedded Processor Ball Interface Group R03 R04 C28 C29 A29 B29 D28 B28 AD33 AC31 AD34 U34 V32 U33 U32 ...
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... PPC440GRx Embedded Processor Table 5. Signals Listed Alphabetically (Sheet 12 of 26) Signal Name [IIC1SClk]SCPClkOut [IIC1SData]SCPDI [IRQ0]GPIO40 [IRQ1]GPIO41 [IRQ2]GPIO42 [IRQ3]GPIO43 [IRQ4]GPIO44[DMAAck1] IRQ5[ModeCtrl][DMAReq1] [IRQ6]GPIO45[EOT1/TC1] [IRQ7]GPIO46[DMAReq0] [IRQ8]GPIO47[DMAAck0] [IRQ9]GPIO48[EOT0/TC0] [LeakTest]HoldPri LeakTest2 MemAddr00 MemAddr01 MemAddr02 MemAddr03 MemAddr04 MemAddr05 MemAddr06 MemAddr07 MemAddr08 MemAddr09 MemAddr10 MemAddr11 MemAddr12 ...
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... MemData16 MemData17 MemData18 MemData19 MemData20 MemData21 MemData22 MemData23 MemData24 MemData25 MemData26 MemData27 MemData28 MemData29 MemData30 MemData31 AMCC Proprietary 440GRx – PPC440GRx Embedded Processor Ball Interface Group AN22 AP22 AM20 AL20 AL22 AM22 AN21 AP21 AP20 AL18 AN17 AP17 AN20 AP19 AN18 ...
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... PPC440GRx Embedded Processor Table 5. Signals Listed Alphabetically (Sheet 14 of 26) Signal Name MemData32 MemData33 MemData34 MemData35 MemData36 MemData37 MemData38 MemData39 MemData40 MemData41 MemData42 MemData43 MemData44 MemData45 MemData46 MemData47 MemData48 MemData49 MemData50 MemData51 MemData52 MemData53 MemData54 MemData55 MemData56 MemData57 MemData58 MemData59 ...
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... Table 5. Signals Listed Alphabetically (Sheet 15 of 26) Signal Name [NFALE]GPIO15 [NFCE0]PerCS0 [NFCE1][PerCS1]GPIO06 [NFCE2][PerCS2]GPIO07 [NFCE3][PerCS3]GPIO08 [NFCLE]GPIO14 [NFRdyBusy]GPIO22 [NFREn]GPIO12 [NFWEn]GPIO13 AMCC Proprietary 440GRx – PPC440GRx Embedded Processor Ball Interface Group B17 D10 B09 D09 D08 NAND Flash A18 A17 D17 A16 ...
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... PPC440GRx Embedded Processor Table 5. Signals Listed Alphabetically (Sheet 16 of 26) Signal Name No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball ...
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... AMCC Proprietary 440GRx – PPC440GRx Embedded Processor Ball Interface Group B05 B12 B23 B30 E02 E06 E07 E09 E17 E26 E28 E29 E33 F05 F30 Power G05 G30 J04 J05 ...
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... PPC440GRx Embedded Processor Table 5. Signals Listed Alphabetically (Sheet 18 of 26) Signal Name PCIAD00 PCIAD01 PCIAD02 PCIAD03 PCIAD04 PCIAD05 PCIAD06 PCIAD07 PCIAD08 PCIAD09 PCIAD10 PCIAD11 PCIAD12 PCIAD13 PCIAD14 PCIAD15 PCIAD16 PCIAD17 PCIAD18 PCIAD19 PCIAD20 PCIAD21 PCIAD22 PCIAD23 PCIAD24 PCIAD25 PCIAD26 PCIAD27 ...
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... PCIGnt5 PCIIDSel PCIINT PCIIRDY PCIPar PCIPErr PCIReq0/Gnt PCIReq1 PCIReq2 PCIReq3 PCIReq4 PCIReq5 PCIReset PCISErr PCIStop PCITRDY AMCC Proprietary 440GRx – PPC440GRx Embedded Processor Ball Interface Group Y34 Y33 Y32 PCI Y31 AA33 AA34 T31 PCI AB34 PCI K33 PCI J32 PCI ...
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... PPC440GRx Embedded Processor Table 5. Signals Listed Alphabetically (Sheet 20 of 26) Signal Name [PerAddr02]GPIO05[EOT3/TC3] [PerAddr03]GPIO04[DMAAck3] [PerAddr04]GPIO03[DMAReq3] [PerAddr05]GPIO02[EOT2/TC2] [PerAddr06]GPIO01[DMAAck2] [PerAddr07]GPIO00[DMAReq2] PerAddr08 PerAddr09 PerAddr10 PerAddr11 PerAddr12 PerAddr13 PerAddr14 PerAddr15 PerAddr16 PerAddr17 PerAddr18 PerAddr19 PerAddr20 PerAddr21 PerAddr22 PerAddr23 PerAddr24 PerAddr25 PerAddr26 PerAddr27 PerAddr28 PerAddr29 ...
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... PerData23 PerData24 PerData25 PerData26 PerData27 PerData28 PerData29 PerData30 PerData31 [PerDataPar0]GPIO36[UART0_CTS/UART3_Rx] [PerDataPar1]GPIO37[UART0_RTS//UART3_Tx] [PerDataPar2]GPIO32 [PerDataPar3]GPIO33 [PerErr]GPIO11 PerOE PerReady AMCC Proprietary 440GRx – PPC440GRx Embedded Processor Ball Interface Group C14 D14 A13 B13 C13 D13 A12 C12 A11 D12 B11 C11 D11 A10 ...
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... PPC440GRx Embedded Processor Table 5. Signals Listed Alphabetically (Sheet 22 of 26) Signal Name PerR/W PerWBE0 PerWBE1 PerWBE2 PerWBE3 PSROOut RAS [RcvrInh]HoldReq RefEn [RejectPkt0]GPIO20 [RejectPkt1]GPIO21 Reserved Reserved Reserved Reserved Reserved Reserved SCPClkOut[IIC1SClk] SCPDI[IIC1SData] [SCPDO]GPIO23 SOV DD SOV DD SOV DD SOV DD SOV DD SOV DD SOV DD SOV ...
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... TrcClk [TrcES0]GPIO52 [TrcES1]GPIO53 [TrcES2]GPIO54 [TrcES3]GPIO55 [TrcES4]GPIO56 [TrcTS0]GPIO57 [TrcTS1]GPIO58 [TrcTS2]GPIO59 [TrcTS3]GPIO60 [TrcTS4]GPIO61 [TrcTS5]GPIO62 [TrcTS6]GPIO63 TRST AMCC Proprietary 440GRx – PPC440GRx Embedded Processor Ball Interface Group Y04 AL10 DDR SDRAM AF04 AL19 AP23 System AD32 System AD31 System P02 JTAG K03 ...
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... PPC440GRx Embedded Processor Table 5. Signals Listed Alphabetically (Sheet 24 of 26) Signal Name [UART0_CTS/UART3_Rx]GPIO36[PerDataPar0] [UART0_DCD/UART1_CTS/UART2_Tx]GPIO34 [UART0_DSR/UART1_RTS/UART2_Rx]GPIO35 [UART0_DTR/UART1_Tx]GPIO38 [UART0_RI/UART1_Rx]GPIO39 [UART0_RTS/UART3_Tx]GPIO37[PerDataPar1] UART0_Rx UARTSerClk UART0_Tx 42 Revision 1.08 – October 15, 2007 Preliminary Data Sheet Ball Interface Group A29 C28 C29 D28 B28 UART Peripheral B29 C27 ...
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... AMCC Proprietary 440GRx – PPC440GRx Embedded Processor Ball Interface Group E11 E12 E13 E14 E15 E20 E21 E22 E23 E24 L05 L30 M05 M30 N05 N16 N19 Power N30 P05 ...
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... PPC440GRx Embedded Processor Table 5. Signals Listed Alphabetically (Sheet 26 of 26) Signal Name Signals in Ball Assignment Order In the following table, only the primary (default) signal name is shown for each ball. Multiplexed or multifunction signals are marked with an asterisk (*) ...
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... B29 A30 PCIAD01 B30 A31 PCIAD03 B31 A32 GND B32 A33 GND B33 A34 GND B34 AMCC Proprietary 440GRx – PPC440GRx Embedded Processor Signal Name Ball Signal Name GND C01 PerData17 GND C02 GND GND C03 GND GND C04 GND OV C05 ...
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... PPC440GRx Embedded Processor Table 6. Signals Listed by Ball Assignment (Sheet Ball Signal Name Ball E01 PerData21 F01 OV E02 F02 DD E03 PerData16 F03 E04 PerData19 F04 E05 GND F05 OV E06 F06 DD OV E07 F07 DD E08 GND F08 OV E09 F09 DD E10 ...
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... J29 No Ball K29 OV J30 K30 DD J31 PCIC1/BE1 K31 J32 PCIPar K32 J33 PCIPErr K33 J34 PCISErr K34 AMCC Proprietary 440GRx – PPC440GRx Embedded Processor Signal Name Ball Signal Name OV GND L01 DD OV TMS L02 DD TDI L03 Reserved OV GND L04 DD V GND ...
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... PPC440GRx Embedded Processor Table 6. Signals Listed by Ball Assignment (Sheet Ball Signal Name Ball N01 GND P01 N02 Reserved P02 N03 Reserved P03 N04 GND P04 V N05 P05 DD N06 No Ball P06 N07 No Ball P07 N08 No Ball P08 N09 No Ball ...
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... V29 OV V30 U30 DD U31 PCIReq1 V31 U32 GPIO46* V32 U33 GPIO45* V33 U34 GPIO43* V34 AMCC Proprietary 440GRx – PPC440GRx Embedded Processor Signal Name Ball Signal Name MemData61 W01 MemData55 MemData60 W02 GND MemData51 W03 MemData54 MemData50 W04 DQS6 SOV W05 ...
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... PPC440GRx Embedded Processor Table 6. Signals Listed by Ball Assignment (Sheet Ball Signal Name Ball AA01 MemData53 AB01 AA02 MemData52 AB02 AA03 MemData43 AB03 AA04 MemData42 AB04 V AA05 AB05 DD AA06 No Ball AB06 AA07 No Ball AB07 AA08 No Ball AB08 AA09 No Ball ...
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... AF29 AE30 GND AF30 AE31 GPIO52* AF31 AE32 GPIO50* AF32 AE33 GPIO51* AF33 AE34 GPIO49* AF34 AMCC Proprietary 440GRx – PPC440GRx Embedded Processor Signal Name Ball Signal Name MemData33 AG01 MemODT1 MemData37 AG02 GND MemData32 AG03 MemData36 SV AG04 MemAddr13 REF2A SOV ...
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... PPC440GRx Embedded Processor Table 6. Signals Listed by Ball Assignment (Sheet Ball Signal Name Ball AJ01 GND AK01 AJ02 WE AK02 AJ03 BA0 AK03 AJ04 RAS AK04 SOV AJ05 AK05 DD AJ06 No Ball AK06 AJ07 No Ball AK07 AJ08 No Ball AK08 AJ09 No Ball ...
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... EOV AN30 AP30 DD AN31 GND AP31 AN32 GND AP32 AN33 GND AP33 AN34 GND AP34 AMCC Proprietary 440GRx – PPC440GRx Embedded Processor Signal Name Ball Signal Name GND GND GND MemAddr01 MemAddr02 MemAddr04 MemAddr09 BA2 ECC7 DQS8 ECC4 MemData26 MemData24 MemData19 ...
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... PPC440GRx has control of the external bus. When during normal operation an external master gains ownership of the external bus, these same pins are used as inputs which are driven by the external master and received by the EBC in the PPC440GRx. In this example, the pins are also bidirectional, serving both as inputs and outputs. ...
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... In 32 bit mode, termination is not needed on the upper data, strobe and mask signals when the DDR I/O and DDR controller are configured for 32 bit mode, SDR0_DDRCFG[64B32B]=0 and DDR0_14[REDUC=1. – Termination of unused ECC signals (ECC0:7, DM8, DQS8) is not needed. AMCC Proprietary 440GRx – PPC440GRx Embedded Processor Table 8. Reserved Pin Connections Pin Connection A05 ...
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... PPC440GRx Embedded Processor Table 9. Signal Functional Description (Sheet Notes: 1. Receiver input has hysteresis 2. Must pull up (recommended value is 3kΩ Must pull down (recommended value is 1kΩ not used, must pull up (recommended value is 3kΩ not used, must pull down (recommended value is 1kΩ) 6. Strapping input during reset ...
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... DDR2 On-die termination enable (not used with DDR1). RAS Row Address Strobe. WE Write Enable. S DDR SDRAM reference voltage 1 input. VREF1A:B S DDR SDRAM reference voltage 2 input. VREF2A:B AMCC Proprietary 440GRx – PPC440GRx Embedded Processor (EOV for Ethernet (EOV for Ethernet Description I/O Type Notes 2 ...
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... PPC440GRx Embedded Processor Table 9. Signal Functional Description (Sheet Notes: 1. Receiver input has hysteresis 2. Must pull up (recommended value is 3kΩ Must pull down (recommended value is 1kΩ not used, must pull up (recommended value is 3kΩ not used, must pull down (recommended value is 1kΩ) 6. Strapping input during reset ...
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... PerCS1:5 External peripheral device select. Used by either peripheral controller or DMA controller depending upon the type of transfer involved. When the PerOE PPC440GRx is the bus master, it enables the selected device to drive the bus. Used by a peripheral slave to indicate it is ready to transfer PerReady data. ...
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... If not used, must pull down (recommended value is 1kΩ) 6. Strapping input during reset; pull-up or pull-down required Signal Name External Master Peripheral Interface Bus Request. Used when the PPC440GRx needs to regain BusReq control of peripheral interface from an external master. External Acknowledgement. Used by the PPC440GRx to ExtAck indicate that a data transfer occurred ...
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... External interrupt requests 6 through 9. JTAG Interface TCK Test Clock. TDI Test Data In. TDO Test Data Out. TMS Test Mode Select. TRST Test Reset. AMCC Proprietary 440GRx – PPC440GRx Embedded Processor (EOV for Ethernet (EOV for Ethernet Description I/O Type Notes O 3 ...
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... PPC440GRx Embedded Processor Table 9. Signal Functional Description (Sheet Notes: 1. Receiver input has hysteresis 2. Must pull up (recommended value is 3kΩ Must pull down (recommended value is 1kΩ not used, must pull up (recommended value is 3kΩ not used, must pull down (recommended value is 1kΩ) 6. Strapping input during reset ...
Page 63
... Ethernet PLLs (analog). DD EAGND Ground for Ethernet PLL voltage (analog). Reserved To avoid noise pickup, the balls on this chip classified as Reserved Reserved must be connected as shown in Table 8 on page 55. AMCC Proprietary 440GRx – PPC440GRx Embedded Processor (EOV for Ethernet (EOV for Ethernet Description ...
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... PPC440GRx Embedded Processor Device Characteristics Table 10. Absolute Maximum Ratings The absolute maximum ratings below are stress ratings only. Operation at or beyond these maximum ratings can cause permanent damage to the device. None of the performance specification contained in this document are guaranteed when operating at these maximum ratings ...
Page 65
... DD 3. The analog voltages used for the on-chip PLLs can be derived from the logic voltage, but must be filtered before entering the PPC440GRx. See “Absolute Maximum Ratings” on page 64. 4. Startup sequencing of the power supply voltages is not required. A power-down cycle must complete (OV before a new power-up cycle is started 5 ...
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... PPC440GRx Embedded Processor Table 12. Input Capacitance Parameter 2.5V/1.8V DDR 3.3V LVTTL PCI 3.3V tolerant CMOS Figure 4. Overshoot Waveform AC Overshoot (V) DC Overshoot (V) DC Undershoot (V) AC Undershoot ( Table 13. Overshoot and Undershoot Receiver AC Overshoot (V) DC Overshoot (V) 3.3V LVTTL 3.9 2.5V (3.3V 3.9 tolerant) 1.2*SOV DDR DD 1.2*OV PCI DD Notes the period of the bus clock. ...
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... The analog voltages (AVdd and EAVdd) used for the on-chip PLLs can be derived from the logic voltage, but must be filtered before entering the PPC440GRx. A Separate filter, as shown below, is recommended for each voltage. • The filter should keep the analog voltage to analog ground compression/expansion due to noise less than +/- 50 mV. • ...
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... PPC440GRx Embedded Processor Table 16. V Supply Power Dissipation DD Frequency (MHz) 400 533 667 Notes: 1. Power is estimated and is based each function with representative traffic. Table 17. DC Power Supply Loads Parameter V (+1.5V) active operating current DD OV (+3.3V) active operating current DD EOV (+2.5V) active operating current DD (+1 ...
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... The following heat sink was used in the above thermal analysis: ALPHA LPD35-15B (35mm x 35mm x15mm) The heat sink is manufactured by: Alpha Novatech, Inc. (www.alphanovatech.com) 473 Sapena Court, #12 Santa Clara, CA 95054 Phone: 408-567-8082 AMCC Proprietary 440GRx – PPC440GRx Embedded Processor Airflow ft/min (m/sec) Symbol 0 100 200 (0) (0 ...
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... PPC440GRx Embedded Processor Thermal Monitor Thermal monitoring of the chip is accomplished using the PNP transistor (β ≈ 2) provided on the chip. The collector of the transistor is connected to ground (GND). The emitter (TherMonA) and base (TherMonB) are connected to chip pins. A voltage measurement (V provides the chip temperature in °K according to the equation: ...
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... The maximum supported processor clock frequency for any part is specified in the part number (see “Ordering and PVR Information” on page 5). Figure 5. Timing Waveform SysClk and GMCRefClk are 2.5V (3.3V tolerant). Slew rate should be measured between 0.7V and 1.7V. Note: AMCC Proprietary 440GRx – PPC440GRx Embedded Processor Min 33.33 15 – 40% of nominal period ...
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... Ethernet operation is unaffected. 3. IIC operation is unaffected. Important the system designer to ensure that any SSCG used with the PPC440GRx meets the above requirements and does not adversely affect other aspects of the system. 72 Revision 1.08 – October 15, 2007 ...
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... GMCRefClk Slew Rate PerClk period PerClk high time PerClk low time UARTSerClk frequency UARTSerClk period UARTSerClk high time UARTSerClk low time AMCC Proprietary 440GRx – PPC440GRx Embedded Processor Min Max – 66.66 15 – 40% of nominal period 60% of nominal period 40% of nominal period 60% of nominal period – ...
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... PPC440GRx Embedded Processor Table 20. Peripheral Interface Clock Timings (continued) Parameter TmrClk frequency TmrClk period TmrClk high time TmrClk low time Notes the period the OPB clock. The internal OPB clock runs at 1/2 the frequency of the PLB clock. The maximum OPB clock OPB frequency is 83 MHz ...
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... Outputs OV High (Drive) Float (High-Z) Valid Low (Drive) RGMII 1000Mb timing is with reference to the raising and falling edge of GMCnTxClk. RGMII 10/100Mb timing is with reference only to the raising edge of GMCnTxClk. AMCC Proprietary 440GRx – PPC440GRx Embedded Processor T T min min min ...
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... PPC440GRx Embedded Processor Table 21. I/O Specifications—All Speeds (Sheet Notes: 1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard. Input (ns) Signal Setup Time Hold Time (T min PCI Interface PCIAD31:00 3 PCIC3:0/BE3:0 3 PCIClk PCIDevSel 5 PCIFrame 5 PCIGnt0:5 n/a PCIIDSel 5 PCIINT n/a PCIIRDY ...
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... SCPClkOut SCPDI 5 SCPDO n/a UARTSerClk UARTn_Rx n/a UARTn_Tx n/a UARTn_DCD n/a UARTn_DSR n/a UARTn_CTS n/a UARTn_DTR n/a UARTn_RI n/a UARTn_RTS n/a Interrupts Interface IRQ0:9 n/a JTAG Interface TCK n/a TDI n/a TDO n/a TMS n/a TRST n/a AMCC Proprietary 440GRx – PPC440GRx Embedded Processor Output (ns) Valid Delay Hold Time min) (T max) (T min n/a n/a 1 n/a n/a n/a 0.5 3.5 n/a 0.5 3.5 1 n/a n/a 1 n/a n/a n/a 0.5 3.5 n/a 0.5 3.5 na ...
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... PPC440GRx Embedded Processor Table 21. I/O Specifications—All Speeds (Sheet Notes: 1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard. Input (ns) Signal Setup Time Hold Time (T min System Interface SysClk TmrClk SysReset n/a Halt n/a SysErr n/a TestEn n/a DrvrInh1:2 n/a RcvrInh n/a GPIO00:11 n/a GPIO12:25 ...
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... BusReq n/a ExtAck n/a ExtReq 4 ExtReset n/a HoldAck n/a HoldReq 4 HoldPri 4 PerClk PerErr 4 NAND Flash Interface NFALE n/a NFCE0:3 n/a NFCLE n/a NFRdyBusy 4 NFREn n/a NFWEn n/a AMCC Proprietary 440GRx – PPC440GRx Embedded Processor Output (ns) Valid Delay Hold Time min) (T max) (T min n n ...
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... The paths (traces) for the data and the associated data strobe signal should be routed with the same length between the PPC440GRx and the SDRAM devices, allowing the rising and falling edges of the strobe to arrive at the capture logic at the same time the data is in transition. All of the following timing assumes a trace velocity of 167ps/in ...
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... PPC440GRx) between the DQS/DQ/DM and the clock (assuming nominal settings as specified in the PPC440GRx Users Manual). While the clock is now 500ps later than the nominal DQS arrival time, this still falls well within the window allowed by the JEDEC spec for T (± ...
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... PPC440GRx Embedded Processor Table 23. DDR SDRAM Output Driver Specifications (Sheet Signal Path RAS CAS WE BankSel0:1 ClkEn DQS0:8 MemODT0:1 DDR SDRAM Write Operation The rising edge of MemClkOut aligns with the first rising edge of the DQS signal on writes. The following data is generated by means of simulation and includes logic, driver, package RLC, and lengths ...
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... Hold time for data signals (minimum time data is valid after rising/falling edge of DSQ Delay from rising/falling edge of clock to the rising/falling edge of DQS DS Note: The timing data in the following tables is based on simulation runs using Einstimer. AMCC Proprietary 440GRx – PPC440GRx Embedded Processor ...
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... PPC440GRx Embedded Processor Table 25. I/O Timing—DDR SDRAM T Notes: 1. All of the DQS signals are referenced to MemClkOut with the DQS delay line programmed to 1 cycle. 2. Clock speed is 166MHz. Signal Name DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8 Table 26. I/O Timing—DDR SDRAM T Notes: 1 ...
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... In order to reliably latch the data into a synchronizing FIFO, the PPC440GRx produces an internal, delayed version of DQS. The amount of delay is user programmable. In the example shown in Figure 12, DDR SDRAM DQS Read Timing, the delay is set to approximately 25% of the system clock. A delay compensation circuit in the PPC440GRx keeps this delay constant. ...
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... PPC440GRx Embedded Processor Initialization The PPC440GRx provides the option for setting initial parameters based on default values or by reading them from a slave PROM attached to the IIC0 bus (see “Serial EEPROM” below). Some of the default values can be altered by strapping on external pins (see “Strapping” below). ...
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... AMCC Proprietary 440GRx – PPC440GRx Embedded Processor Contents of Modification Initial creation of document. Correct security designation. Add new/updated power and current values. Correct list containing balls by ball number. Update power and temperature data. Add clocking information. Update EEPROM. ...
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... PPC440GRx Embedded Processor 215 Moffett Park Drive, Sunnyvale, CA 94089 Phone: (408) 542-8600 — (800) 840-6055 — Fax: (408) 542-8601 AMCC reserves the right to make changes to its products, its data sheets, or related documentation, without notice and warrants its products solely pursuant to its terms and conditions of sale, only to substantially comply with the latest available data sheet. Please consult AMCC’ ...