PPC440GRX-NPAFFFTS AMCC [Applied Micro Circuits Corporation], PPC440GRX-NPAFFFTS Datasheet - Page 57

• Manufacturer Part Number: PPC440GRX-NPAFFFTS
• Description: PowerPC 440GRx Embedded Processor
• Manufacturer: AMCC [Applied Micro Circuits Corporation]

Revision 1.08 – October 15, 2007
Table 9. Signal Functional Description (Sheet 2 of 8)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to OV
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to OV
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required
AMCC Proprietary
Preliminary Data Sheet
DDR2/1 SDRAM Interface
BA0:2
BankSel0:1
CAS
ClkEn
DM0:7
DM8
DQS0:7
DQS8
ECC0:7
MemAddr00:13
MemData00:63
MemClkOut
MemClkOut
MemODT0:1
RAS
WE
S
S
VREF1A:B
VREF2A:B
Signal Name
Bank Address supporting up to eight internal banks.
Clock Enable.
Memory data bus (MemData32:63 available for DDR2 only).
DDR2 On-die termination enable (not used with DDR1).
Selects up to two external DDR SDRAM banks.
Column Address Strobe.
Memory write data byte lane masks. DM8 is the byte lane
mask for the ECC byte lane.
Byte lane data strobe.
Byte lane data strobe for ECC.
ECC check bits 0:7.
Memory address bus.
Subsystem clock.
Row Address Strobe.
Write Enable.
DDR SDRAM reference voltage 1 input.
DDR SDRAM reference voltage 2 input.
DD
(EOV
Description
DD
DD
for Ethernet)
440GRx – PPC440GRx Embedded Processor
(EOV
DD
for Ethernet)
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
I
I
(1.25V or 0.9V)
(1.25V or 0.9V)
Volt ref receiver
SDRAM-DDR
SDRAM-DDR
SDRAM-DDR
SDRAM-DDR
SDRAM-DDR
SDRAM-DDR
SDRAM-DDR
SDRAM-DDR
SDRAM-DDR
SDRAM-DDR
SDRAM-DDR
SDRAM-DDR
SDRAM-DDR
Volt ref driver
2.5V (1.8V)
2.5V (1.8V)
2.5V (1.8V)
2.5V (1.8V)
2.5V (1.8V)
2.5V (1.8V)
2.5V (1.8V)
2.5V (1.8V)
2.5V (1.8V)
2.5V (1.8V)
2.5V (1.8V)
2.5V (1.8V)
2.5V (1.8V)
Diff driver
Type
Notes
57