PPC440GRX-NPAFFFTS AMCC [Applied Micro Circuits Corporation], PPC440GRX-NPAFFFTS Datasheet - Page 55

• Manufacturer Part Number: PPC440GRX-NPAFFFTS
• Description: PowerPC 440GRx Embedded Processor
• Manufacturer: AMCC [Applied Micro Circuits Corporation]

Revision 1.08 – October 15, 2007
Multimode Signals
In some cases (for example, Ethernet) the function of a pin may vary with different modes of operation. When a pin
has multiple signal names assigned to distinguish different modes of operation, all of the names are shown.
Strapping Pins
One group of pins is used as strapped inputs during system reset. These pins function as strapped inputs only
during reset and are used for other functions during normal operation (see “Strapping” on page 86). Note that
these are not multiplexed pins since the function of the pins is not programmable.
Reserved Pins
The pins classified as Reserved are not functional and must be connected as shown in Table 8.
Unused I/Os
Termination of unused receivers is generally required; however, there are some exceptions that reduce or
eliminate the need for termination.
AMCC Proprietary
Preliminary Data Sheet
Signals Multiplexed with GPIO:
By default after reset, signals shared with GPIO pins are configured as GPIO receivers. Termination however,
is not needed if the GPIO during initialization are configured as outputs. To configure as drivers, set and clear
the appropriate bits in the GPIOx_ODR, GPIOx_TCR and GPIOx_OR registers as described in the GPIO
chapter of the user’s manual.
PCI:
When the PCI bridge is unused, configure the PCI controller to park on the bus by pulling the PCIReq0[Gnt]
signal low. Parking forces the PLB3 to PCI bridge to actively drive PCIAD31:0 and PCIC3:0[BE3:0]. The
remaining PCI control signals must be terminated as follows:
DDR:
– Disable the internal PCI arbiter and enable PCI sychronous mode (See IIC Boot Strap Chapter in the
– Individually connect PCISErr, PCIPErr, PCITRDY, and PCISTOP through 3k
– Individually connect PCIReq1:5 through 3k
– Connect PCIReq0[Gnt] through 1k
– In 32 bit mode, termination is not needed on the upper data, strobe and mask signals when the DDR I/O
– Termination of unused ECC signals (ECC0:7, DM8, DQS8) is not needed.
User’s Manual).
Note:
terminating an unused PCI interface).
and DDR controller are configured for 32 bit mode, SDR0_DDRCFG[64B32B]=0 and
DDR0_14[REDUC=1.
Synchronous mode is not supported when operating the PCI bus. This mode should only be used for
Table 8. Reserved Pin Connections
Ω
resistor to GND.
A05
N02
N03
J01
J02
L03
Pin
Ω
resistors to +3.3V.
440GRx – PPC440GRx Embedded Processor
Connection
OV
Open
Open
GND
GND
GND
DD
Ω
resistors to +3.3V.
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