PPC440GRX-NPAFFFTS AMCC [Applied Micro Circuits Corporation], PPC440GRX-NPAFFFTS Datasheet - Page 54

• Manufacturer Part Number: PPC440GRX-NPAFFFTS
• Description: PowerPC 440GRx Embedded Processor
• Manufacturer: AMCC [Applied Micro Circuits Corporation]

440GRx – PPC440GRx Embedded Processor
Signal Descriptions
The PPC440GRx embedded controller is packaged in a 456-ball enhanced plastic ball grid array (E-PBGA). The
following tables describe the package level pinout.
In the Table 9 on page 56, each I/O signal is listed along with a short description of its function. Active-low signals
(for example, RAS) are marked with an overline. Please see Table 5 on page 19 for the pin (ball) number to which
each signal is assigned.
Multiplexed Signals
Some signals are multiplexed on the same pin so that the pin can be used for different functions. In most cases,
the signal names shown in this table are not accompanied by signal names that may be multiplexed on the same
pin. If you need to know what, if any, signals are multiplexed with a particular signal, look up the name in Table 5
on page 19. It is expected that in any single application a particular pin will always be programmed to serve the
same function. The flexibility of multiplexing allows a single chip to offer a richer pin selection than would otherwise
be possible.
Multipurpose Signals
In addition to multiplexing, some pins are also multi-purpose. For example, the EBC peripheral controller address
pins (PerAddr) are used as outputs by the PPC440GRx to broadcast an address to external slave devices when
the PPC440GRx has control of the external bus. When during normal operation an external master gains
ownership of the external bus, these same pins are used as inputs which are driven by the external master and
received by the EBC in the PPC440GRx. In this example, the pins are also bidirectional, serving both as inputs and
outputs.
54
Note:
the GPIO registers for the desired function as described in the GPIO chapter of the user’s manual. Any of these signals
requiring a particular state prior to running initialization code must be terminated wit pull ups or pull downs
Signals multiplexed with GPIO default to GPIO receivers and float after reset. Initialization software must configure
Table 7. Pin Summary
Signal pins, non-multiplexed
Signal pins, multiplexed
Total Signal Pins
Total Power Pins
Total Pins
Reserved
EAGND
Group
SOV
EOV
EAV
AGND
AV
OV
GND
V
DD
DD
DD
DD
DD
DD
No. of Pins
268
361
197
313
680
93
30
14
12
56
1
1
1
1
6
Revision 1.08 – October 15, 2007
Preliminary Data Sheet
AMCC Proprietary
.